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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 38/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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6.42
43
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
JTAG Identification Register Definitions
JTAG InterfaceSpecification
Instruction Field
Value
Description
Revision Number (31:28)
0x1
Reserved for version number
IDT Device ID (27:12)
0x200
Defines IDT part number
IDT JEDEC ID (11:1)
0x33
Allows unique identification of device vendor as IDT
ID Register Indicator Bit (Bit 0)
1
Indicates the presenc e of an ID register
I5325 tbl 02
Instruction
Description
O P CO DE
EXTEST(3)
Fo rc e s co nte nts o f the b o und ary scan ce lls o nto the d e vice o utp uts
(1,3).
P lac es the bo und ary s c an re gis te r (B S R ) b e twee n TD I and TD O .
0000
SAM PLE /PRELO A D
P lac es the bo und ary s c an re gis te r (B S R ) b e twee n TD I and TD O .
S A M P LE allo ws d ata from dev ic e inputs
(2) and o utp uts(1) to b e captured
in the b o und ary s c an c e lls and shifte d s e rially thro ug h TDO . P RE LO A D
allo w s d ata to b e inp ut s e rially into the b o und ary s c an c e lls v ia the TDI.
0001
DE V IC E _ID
Lo ad s the J TA G ID re gis te r (J IDR) with the v e nd o r ID c ode and plac e s
the re gis ter be twe e n TDI and TDO .
0010
HIG HZ
P lac es the by pas s re g is te r (B Y R) be tween TDI and TDO . F o rc es all
dev ic e o utp ut driv ers to a H ig h-Z s tate.
0011
RE S E RV E D
S e v e ral c o m b inatio ns are re s e rv e d . Do n o t us e c o d e s o the r than tho s e
id e ntifie d fo r EXTEST, SA M P LE /P RE LO AD, D EVICE _ID, HIG H Z, CLA M P,
VA LIDATE and BYPASS ins tructio ns .
0100
RE S E RV E D
0101
RE S E RV E D
0110
RE S E RV E D
0111
CLA M P
Us e s B Y R . Fo rc e s co nte nts o f the b o und ary scan ce lls o nto the d e vice
outp uts . P lac e s the by p as s re g is te r (B Y R ) be tween TDI and TD O .
1000
RE S E RV E D
S am e as abov e.
1001
RE S E RV E D
1010
RE S E RV E D
1011
RE S E RV E D
1100
VA LIDATE
A uto m atically lo ad e d into the instructio n re g iste r whe ne ve r the TA P
c o ntro lle r pas s e s thro ug h the C A P TU RE -IR s tate. The lo w e r two bits '01'
are m and ate d b y the IE E E s td . 1149.1 s p e c ific atio n.
1101
RE S E RV E D
S am e as abov e.
1110
BYPA S S
The B Y PA S S ins truc tio n is u s e d to trunc ate the b o und ary s c an re g is te r
as a sing le b it in le ng th.
1111
I5325 tbl 04
Available JTAG Instructions
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS and
TRST.
3. The IDT75T43100 supports a user-designed Bidirectional Boundary Scan Cell, in compliance with IEEE Standard 1149.1b-1994, for each of the REQDATA
signals. When using these Bidirectional cells acting as outputs, while EXTEST is in effect, the capture flip-flop loads a 0 (ZERO) data at the CAPTURE-DR
state. Refer to the Boundary Scan Descriptive Language (BSDL) file for a detailed description of the cell.
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相关代理商/技术参数 |
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| IDT76BDLS01200INA | 制造商:Integrated Device Technology Inc 功能描述:BOARD EVALUATION |
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