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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 43/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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6
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Signal Descriptions continued
Symbol
Pin Function
# Pins
I/O
Description
Depth Expansion:
MATCHOUT
Match
Output
1Output
Match Output is an active high signal that is driven one cycle before the Index is driven on the
bus. This signal signifies that a match has occurred in the IPC. The Match Output signal is active
high and is fed into a Match Input line of all lower priority IPC(s).The Match Output signal is
reference to 2.5V operating characteristic, regardless of selected VDDQ.
MATCHIN
Match
Input
7
Input
The Match Input signal is driven by all upstream Match Output signals. This indicates to all down
stream IPCs that a hit in a higher priority IPC has occurred. This will prevent a lower priority IPC
from driving the Index bus if a higher priority IPC encountered a match.
JTAG Signals:
TMS
Test Mode
Select
1
Input
JTAG instruction input. This is 1149 compliant and has Input levels the same as the other input
pins of the device. If set at 2.5V or 3.3V VDDQ This pin has an internal pullup
TDI
Test Data Input
1
Input
JTAG data input. This pin has an internal pullup
TDO
Test Data
Output
1
Output
Tristate
JTAG Data output pin. This pin is driven on the high to low edge of Test Clock.
TCK
Test Clock
1
Input
A maximum of 10Mhz test clock. This pin has an internal pullup
TRST
JTAG Reset
1
Input
Asynchronous JTAG Reset. This is an active low signal that will reset only JTAG associated
logic. This will have no affect on the other IPC functional logic. This pin has an internal pullup
Power Supply:
VDD
Core Power
29
Supply
2.5V core power supply pins for the device
VDDQ
I/O Power
26
Supply
2.5V or 3.3V I/O supply voltages for the device
VMATCH
Match Power
46
Supply
1.5V match supply voltage for the device
VDDQ Select
I/O Power
1
Input
This is a DC signal that defines the output drive to be either 3.3V or 2.5V. To select 3.3V output
drive set VDDQ Select Low (Vss), for 2.5V output drive set VDDQ Select High (VDDQ).
Vss
Ground
69
Supply
Common gro und pins for IPC supply voltages
Other:
DNU
Do Not Use
9
N/A
Do not connect these pins
NC
No Connect
1
N/A
This p in is not conne cted to the d ie, can be left floating or connected to Vss to minimize thermal
impedance
B5325 tbl 01a
Signal Descriptions and Pinout
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