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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 8/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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16
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Bus Description
The IPC utilizes the Command Bus to load the specific operational
instructions. TheCommandBusisa7-bitbuswhichisusedtospecifythe
operation of the IP Co-Processor.
TheIPCutilizestwobusinterfacesfordataflow:theRequestBus,and
theIndexBus. TheRequestBusisa72-bitbususedforreadingandwriting
IPC entries and presenting Lookup data to the device. The Index Bus is
a 20-bit bus, which is used to drive the result of the Lookup (or Index) to
either a SRAM or an ASIC.
x
x Command Bus
x
x Request Bus
x
x Index Bus
Table 3.0 Instruction Set
CM D [3:0]
Instruction
0010
x 72 Lo o k up
P e rfo rm s a x 72 lo ok up in the IP C array.
0011
x 144 Lo o k up
P e rform s a x 144 look up in the IP C array.
0100
Write
W rite to Data ce lls, W rite to M ask Ce lls,
W rite to Regis ters , W rite to E x te rnal S RA M
0101
Re ad
Re ad s o f D ata ce lls, Re ad o f M ask Ce lls ,
Re ad of Regis ters , Re ad of E x te rnal S RA M
1010
x 288 Lo o k up
P e rform s a x 288 look up in the IP C array.
1011
SRA M No
Wait Re ad
This instructio n allo ws fo r a d ire ct ac ce ss to
the as s o c iate d S RA M on the Index B us . In
this case no ac ce ss to th e IP C co re will b e
m ad e . A n ac c e s s thro ug h this p ath will
mimic the s ame d e lay s o f the IP C to allo w
fo r S RA M ac c e s s e s to be pipelined with
re s t o f the IP C func tio ns .
XXXX
Re s e rv e d
A ll o the r b it c o m b inatio ns are re s e rv e d .
E5 325 tbl 02
64 3
0
GMR and SRR Select
Instruction
E5325 tbl 01
Figure 3.0 Command Bus Format
Bus Description & Command Bus Format
Command Bus
The Command Bus is used to specify the operation of the IP Co-
Processor. It is divided into two fields, as illustrated in Fig 3.0. The
Instruction field (CMD[3:0]) is used to designate the required Lookup,
Write, Read or the SRAM No Wait Read. The GMR and SRR Select field
(CMD[6:4]) is used to access both a Global Mask Register and a Search
Result Register for the requested Lookup.
Instruction Field
The Instruction field consists of 4 bits, and defines 6 commands as
shown in Table 3.0. The Lookup commands are operational in nature,
whereas the Read, Write and SRAM No Wait Read commands are
primarily used for table maintenance. The operational commands utilize
additional bits in the Command Bus to define the Search Result Register
andGlobalMaskRegister,whilethemaintenancecommandsignorethese
additional bit fields. However, there is one exception when doing a Write
InstructiontotheDataorMaskcells,theadditionalbitsCMD[6:4]areused
to select the Global Mask Registers. As with all CMOS inputs these pins
should always be driven (or pulled up), and never be left floating.
GMR and SRR Select Field
The GMR and SRR select field consists of 3 bits that define which of
the Global Mask Register and Search Result Register are used. Table
3.1 defines which GMRs can be selected for each Lookup mode. Table
3.2 defines which SRRs can be selected to store the Index result.
A Request Strobe is used to define the start of an IPC operation
sequence. Please refer to the "Instruction/Command Bus Timing
Diagrams" which illustrates the timing for a generic IPC operation.
Additional signals are also provided for initialization, SRAM controls and
for depth expansion.
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