参数资料
| 型号： | ISL62773IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL62773
Theory of Operation
Multiphase R 3 ? Modulator
The ISL62773 is a multiphase regulator implementing two voltage
regulators, CORE VR and Northbridge (NB) VR, on one chip
controlled by AMD’s? SVI2? protocol. The CORE VR can be
programmed for 1-, 2- or 3-phase operation. The Northbridge VR
can be configured for 1- or 2-phase operation. Both regulators use
the Intersil patented R 3 ? (Robust Ripple Regulator) modulator.
The R 3 ? modulator combines the best features of fixed frequency
PWM and hysteretic PWM while eliminating many of their
shortcomings. Figure 7 conceptually shows the multiphase R 3 ?
modulator circuit, and Figure 8 shows the operation principles.
VW
VCRM
COMP
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
HYSTERETIC
WINDOW
VW
MASTER CLOCK CIRCUIT
MASTER
PWM2
MASTER
CLOCK
COMP
VCRM
CLOCK
PHASE
SEQUENCER
CLOCK1
CLOCK2
CLOCK3
CLOCK3
GMVO
CRM
PWM3
VW
VCRS1
GM
SLAVE CIRCUIT 1
CLOCK1 S PWM1
Q
R
PHASE1
L1
I L1
VO
CO
VW
VCRS2
VCRS3
VCRS1
CRS1
VW
SLAVE CIRCUIT 2
CLOCK2 S PWM2
Q
R
PHASE2
L2
I L2
FIGURE 8. R 3 ? MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
Each slave circuit has its own ripple capacitor C rs , whose voltage
mimics the inductor ripple current. A g m amplifier converts the
inductor voltage into a current source to charge and discharge
CRS2
VCRS2
VW
GM
CLOCK3
SLAVE CIRCUIT 3
S PWM3
Q
R
PHASE3
L3
I L3
C rs . The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C rs . When C rs
voltage V Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C rs .
Since the controller works with V crs , which are large amplitude
and noise-free synthesized signals, it achieves lower phase jitter
CRS3
VCRS3
GM
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL62773 to maintain a 0.5% output
voltage accuracy.
FIGURE 7. R 3 ? MODULATOR CIRCUIT
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C rm with a current source equal
to g m V o , where g m is a gain factor. C rm voltage V CRM is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the CORE VR is in 3-
phase mode, the master clock signal is distributed to the three
phases, and the Clock 1~3 signals will be 120° out-of-phase. If
the Core VR is in 2-phase mode, the master clock signal is
distributed to Phases 1 and 2, and the Clock1 and Clock2 signals
will be 180° out-of-phase. If the Core VR is in 1-phase mode, the
master clock signal will be distributed to Phase 1 only and be the
Clock1 signal.
14
Figure 9 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL62773 excellent
response speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
March 7, 2012
FN8263.0
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相关代理商/技术参数 |
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| ISL6277A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0 |
| ISL6277AHRZ | 制造商:Intersil Corporation 功能描述:MULTI-OUTPUT CONTROLLER FOR AMD FUSION UP, 6X6 QFN - Rail/Tube 制造商:Intersil Corporation 功能描述:IC PWM REG MULTIPH AMD 48-QFN 制造商:Intersil 功能描述:PWM Regulator for AMD Fusion |
| ISL6277AHRZ-T | 制造商:Intersil Corporation 功能描述:MULTI-OUTPUT CONTROLLER FOR AMD FUSION UP, 6X6 QFN, T&R - Tape and Reel 制造商:Intersil Corporation 功能描述:IC PWM REG MULTIPH AMD 48-QFN 制造商:Intersil 功能描述:PWM Regulator --- for AMD Fusion--- |
| ISL6277AIRZ | 功能描述:电流型 PWM 控制器 Multi-output Controller for AMD fusion uP, 6X6 QFN RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6277AIRZ-T | 功能描述:电流型 PWM 控制器 Multi-output Controller for AMD fusion uP, 6X6 QFN, T&R RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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