参数资料
| 型号： | ISL62773IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 31/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL62773
Substitution of Equation 28 and rewriting Equation 34, or
substitution of Equation 32 and rewriting Equation 35, gives the
same result as in Equation 36:
Q1
L
V O
R droop = ---------------- ? LL
I o
I droop
(EQ. 36)
V IN
GATE
DRIVER
Q2
C OUT
i O
?
-
One can use the full-load condition to calculate R droop . For
example, given I omax = 65A, I droopmax = 45μA and LL = 2.1m ? ,
Equation 36 gives R droop = 3.03k ? .
It is recommended to start with the R droop value calculated by
Equation 36 and fine-tune it on the actual board to get accurate
MOD.
COMP
LOAD LINE SLOPE
20
EA
+
+
+
load-line slope. One should record the output voltage readings at
VID
ISOLATION
no load and at full load for load-line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Compensator
LOOP GAIN =
CHANNEL B
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
TRANSFORMER
CHANNEL B
EXCITATION OUTPUT
Figure 23 shows the desired load transient response waveforms.
Figure 29 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Z out (s). If Z out (s) is equal to the
load-line slope LL, i.e., a constant output impedance, then in the
entire frequency range, V o will have a square response when I o
has a square change.
FIGURE 30. LOOP GAIN T1(s) MEASUREMENT SET-UP
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s), therefore
has a higher impact on system stability.
T2(s) is the voltage loop gain with closed droop loop, thus having
a higher impact on output voltage response.
Design the compensator to get stable T1(s) and T2(s) with sufficient
Z out (s) = LL
i
o
phase margin and an output impedance equal to or smaller than
the load-line slope.
VID
VR
LOAD
V
o
L
V O
Q1
V IN
GATE
DRIVER
Q2
C O
I O
FIGURE 29. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
Intersil provides a Microsoft Excel-based spreadsheet to help
LOAD LINE SLOPE
design the compensator and the current sensing network so that
VR achieves constant output impedance as a stable system.
MOD.
EA
-
+
+
20
?
+
VID
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop, which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 30 conceptually
shows T1(s) measurement set-up, and Figure 31 conceptually
LOOP GAIN =
COMP
CHANNEL B
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
ISOLATION
TRANSFORMER
CHANNEL B
EXCITATION OUTPUT
shows T2(s) measurement set-up. The VR senses the inductor
current, multiplies it by a gain of the load-line slope, adds it on top
of the sensed output voltage, and then feeds it to the
compensator. T1 is measured after the summing node, and T2 is
measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can actually be measured on an ISL62773 regulator.
31
FIGURE 31. LOOP GAIN T2(s) MEASUREMENT SET-UP
Current Balancing
Refer to Figures 15 through 22 for information on current
balancing. The ISL62773 achieves current balancing through
matching the ISEN pin voltages. R isen and C isen form filters to
remove the switching ripple of the phase node voltages. It is
recommended to use a rather long R isen C isen time constant such
that the ISEN voltages have minimal ripple and represent the DC
current flowing through the inductors. Recommended values are
R s = 10k ? and C s = 0.22μF.
March 7, 2012
FN8263.0
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