参数资料
| 型号： | ISL62773IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 17/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL62773
Rdroop
VCC SENSE + V
droop
= V DAC + VSS SENSE
(EQ. 3)
Vdroop
FB
+ -
Idroop
VCC SENSE
VR LOCAL VO
“CATCH” RESISTOR
Rewriting Equation 3 and substituting Equation 2 gives
Equation 4 is the exact equation required for load-line
implementation.
SVD
COMP
+
E/A
-
INTERNAL TO IC
?
+
VDAC
DAC
X1
+
-
SVC
SVID[7:0]
RTN
VSS SENSE
VSS
“CATCH” RESISTOR
VCC SENSE – VSS SENSE = V DAC – R droop ? ? I droop ? 5 ? 4 ?
(EQ. 4)
The VCC SENSE and VSS SENSE signals come from the processor die.
The feedback is open circuit in the absence of the processor. As
Figure 14 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and to add
another “catch” resistor to connect the VR local output ground to the
FIGURE 14. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output voltage
droops from the VID programmed value by an amount
RTN pin. These resistors, typically 10 ? ~100 ? , provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
proportional to the load current, to achieve the load line. The
ISL62773 can sense the inductor current through the intrinsic DC
PHASE3
L3
R dcr3
R pcb3
Resistance (DCR) of the inductors (see Figures 3 and 4) or
through resistors in series with the inductors (see Figure 5). In
both methods, capacitor C n voltage represents the total inductor
current. A droop amplifier converts C n voltage into an internal
current source with the gain set by resistor R i . The current source
is used for load line implementation, current monitoring and
overcurrent protection.
ISEN3
INTERNAL
TO IC
ISEN2
R isen
C isen
PHASE2
R isen
C isen
L2
L1
I L3
I L2
R dcr2
R dcr1
R pcb2
R pcb1
V O
Figure 14 shows the load-line implementation. The ISL62773
drives a current source (I droop ) out of the FB pin, as described by
Equation 1.
ISEN1
PHASE1
R isen
C isen
I L1
I droop = -----------
V Cn
R i
(EQ. 1)
FIGURE 15. CURRENT BALANCING CIRCUIT
The ISL62773 monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 15
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load-line accuracy with
reduced cost.
I droop flows through resistor R droop and creates a voltage drop as
shown in Equation 2.
shows the recommended current balancing circuit for DCR
sensing. Each phase node voltage is averaged by a low-pass filter
consisting of R isen and C isen , and is presented to the
corresponding ISEN pin. R isen should be routed to the inductor
phase-node pad in order to eliminate the effect of phase node
parasitic PCB DCR. Equations 5 through 7 give the ISEN pin
voltages:
V droop = R droop ? ? I droop ? --- ?
? 4 ?
5
(EQ. 2)
V ISEN1 = ? R dcr1 + R pcb1 ? ? I L1
(EQ. 5)
V ISEN3 = ? R dcr3 + R pcb3 ? ? I L3
V droop is the droop voltage required to implement load line.
Changing R droop or scaling I droop can change the load line slope.
Since I droop also sets the overcurrent protection level, it is
recommended to first scale I droop based on OCP requirement.
Next, select an appropriate R droop value to obtain the desired
load line slope.
Differential Sensing
Figure 14 also shows the differential voltage sensing scheme.
VCC SENSE and VSS SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSS SENSE voltage and adds it to the DAC output. The error
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 3:
17
V ISEN2 = ? R dcr2 + R pcb2 ? ? I L2 (EQ. 6)
(EQ. 7)
where R dcr1 , R dcr2 and R dcr3 are inductor DCR; R pcb1 , R pcb2
and R pcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and I L1 , I L2 and I L3 are
inductor average currents.
The ISL62773 will adjusts the phase pulse-width relative to the
other phases to make V ISEN1 = V ISEN2 = V ISEN3 , thus to achieve
I L1 = I L2 = I L3 , when R dcr1 = R dcr2 = R dcr3 and
R pcb1 = R pcb2 = R pcb3 .
March 7, 2012
FN8263.0
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