参数资料
| 型号： | ISL62773IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 22/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL62773
.
SVC
TABLE 6. PRE-PWROK METAL VID CODES
SVD OUTPUT VOLTAGE (V)
If the PWROK input is de-asserted, then the controller steps both
the Core and the Northbridge VRs back to the stored pre-PWROK
metal VID level in the holding register from initial soft-start. No
0
0
1
1
0
1
0
1
1.1
1.0
0.9
0.8
attempt is made to read the SVC and SVD inputs during this time.
If PWROK is re-asserted, then the ISL62773 SVI interface waits
for instructions.
If ENABLE goes low during normal operation, all external
MOSFETs are tri-stated and both PGOOD and PGOOD_NB are
Once the programming pins are read, the internal DAC circuitry
begins to ramp Core and Northbridge VRs to the decoded
pre-PWROK Metal VID output level. The digital soft-start circuitry
ramps the internal reference to the target gradually at a fixed
rate of approximately 5mV/μs until the output voltage reaches
~250mV and then at the programmed slew rate. The controlled
ramp of all output voltage planes reduces in-rush current during
the soft-start interval. At the end of the soft-start interval, the
PGOOD and PGOOD_NB outputs transition high, indicating both
output planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL62773 tri-states both outputs. PGOOD and PGOOD_NB are
pulled low with the loss of ENABLE. The Core and Northbridge VR
output voltages decay, based on output capacitance and load
leakage resistance. If bias to VDD falls below the POR level, the
ISL62773 responds in the manner previously described. Once
VDD and ENABLE rise above their respective rising thresholds,
the internal DAC circuitry re-acquires a pre-PWROK metal VID
code, and the controller soft-starts.
SVI Interface Active
Once the Core and Northbridge VRs have successfully
soft-started and PGOOD and PGOOD_NB signals transition high,
PWROK can be asserted externally to the ISL62773. Once
PWROK is asserted to the IC, SVI instructions can begin as the
controller actively monitors the SVI interface. Details of the SVI
Bus protocol are provided in the “AMD Serial VID Interface 2.0
(SVI2) Specification”. See AMD publication #48022.
Once a VID change command is received, the ISL62773 decodes
the information to determine which VR is affected and the VID
target is determined by the byte combinations in Table 7. The
internal DAC circuitry steps the output voltage of the VR
commanded to the new VID level. During this time, one or more
of the VR outputs could be targeted. In the event either VR is
commanded to power-off by serial VID commands, the PGOOD
signal remains asserted.
22
pulled low. This event clears the pre-PWROK metal VID code and
forces the controller to check SVC and SVD upon restart, storing
the pre-PWROK metal VID code found on restart.
A POR event on either VCC or VIN during normal operation shuts
down both regulators, and both PGOOD outputs are pulled low.
The pre-PWROK metal VID code is not retained.
VID-on-the-Fly Transition
Once PWROK is high, the ISL62773 detects this flag and begins
monitoring the SVC and SVD pins for SVI instructions. The
microprocessor follows the protocol outlined in the following
sections to send instructions for VID-on-the-fly transitions. The
ISL62773 decodes the instruction and acknowledges the new
VID code. For VID codes higher than the current VID level, the
ISL62773 begins stepping the commanded VR outputs to the
new VID target with the slew rate programmed by the FCCM_NB
resistor.
When the VID codes are lower than the current VID level, the
ISL62773 checks the state of power state bits in the SVI
command. If power state bits are not active, the controller begins
stepping the regulator output to the new VID target. If the power
state bits are active, the controller allows the output voltage to
decay and slowly steps the DAC down with the natural decay of
the output. This allows the controller to quickly recover and move
to a high VID code if commanded.
SVI Data Communication Protocol
The SVI WIRE protocol is based on the I 2 C bus concept. Two wires
[serial clock (SVC) and serial data (SVD)], carry information
between the AMD processor (master) and VR controller (slave) on
the bus. The master initiates and terminates SVI transactions
and drives the clock, SVC, during a transaction. The AMD
processor is always the master, and the voltage regulators are
the slaves. The slave receives the SVI transactions and acts
accordingly. Mobile SVI WIRE protocol timing is based on
high-speed mode I 2 C. See AMD publication #48022 for
additional details.
March 7, 2012
FN8263.0
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