参数资料
| 型号： | ISL62773IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL62773
Floating DriverX and PWM_Y Configuration
The ISL62773 allows for one internal driver and one PWM output
to be configured to opposite VRs depending on the desired
configuration of the Northbridge VR. Internal DriverX can be used
as Channel 1 of the Northbridge VR with PWM_Y used for
Channel 3 of the Core VR. Using this partitioning, a 2+1 or 1+1
configured ISL62773 would not require an external driver.
If routing of the driver signals would be a cause of concern due to
having an internal driver on the Northbridge VR, then the
ISL62773 can be configured to use PWM_Y as Channel 1 on the
Northbridge VR. DriverX would then be used as Channel 3 of the
Core VR. This allows the placement of the external drivers for the
Northbridge VR to be closer to the output stage(s) depending on
the number of active Phases. Providing placement and layout
flexibility to the Northbridge VR.
TABLE 4. FCCM_NB RESISTOR SELECTION
Slew Rate for Core
CCM Switching Frequency
The Core and Northbridge VR switching frequency is set by the
programming resistors on COMP_NB and FCCM_NC. When the
ISL62773 is in continuous conduction mode (CCM), the switching
frequency is not absolutely constant due to the nature of the R 3 ?
insertion and decreases during load release to achieve fast
response. Thus, the switching frequency is relatively constant at
steady state. Variation is expected when the power stage
condition, such as input voltage, output voltage, load, etc.
changes. The variation is usually less than 10% and does not
have any significant effect on output voltage ripple magnitude.
Table 5 defines the switching frequency based on the resistor
values used to program the COMP_NB and FCCM_NB pins. Use
Tables 3 and 4 to determine the correct resistor value in these
ranges to program the desired output offset, Slew Rate and
DriverX/PWM_Y configuration.t
RESISTOR VALUE
[ k ? ]
5.62
and Northbridge
[mV/ ? s]
20
DriverX
PWM_Y
TABLE 5. SWITCHING FREQUENCY SELECTION
FREQUENCY COMP_NB FCCM_NB
[kHz] RANGE [k ? ] RANGE [k ? ]
9.53
13.3
15
12.5
300
57.6 to OPEN
21.0 to 41.2
or
154 to OPEN
16.9
21.0
26.7
34.0
10
20
15
12.5
Core VR
Channel 3
NB VR
Channel 1
350
400
5.62 to 41.2
57.6 to OPEN
21.0 to 41.2
or
154 to OPEN
5.62 to 16.9
or
41.2
10
57.6 to 121
57.6
73.2
20
15
450
5.62 to 41.2
5.62 to 16.9
or
57.6 to 121
95.3
12.5
121
154
182
221
OPEN
10
20
15
12.5
10
NB VR
Channel 1
Core VR
Channel 3
The controller monitors SVI commands to determine when to
enter power-saving mode, implement dynamic VID changes and
shut down individual outputs.
AMD Serial VID Interface 2.0
The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the
AMD processor to directly control the Core and Northbridge
voltage reference levels within the ISL62773. Once the PWROK
VID-on-the-Fly Slew Rate Selection
The FCCM_NB resistor is also used to select the slew rate for VID
changes commanded by the processor. Once selected, the slew
rate is locked in during soft-start and is not adjustable during
operation. The lowest slew rate which can be selected is
10mV/μs, which is above the minimum of 7.5mV/μs required by
the SVI2 specification. The slew rate selected sets the slew rate
for both Core and Northbridge VRs, thus they cannot be
independently selected.
21
signal goes high, the IC begins monitoring the SVC and SVD pins
for instructions. The ISL62773 uses a digital-to-analog converter
(DAC) to generate a reference voltage based on the decoded SVI
value. See Figure 12 for a simple SVI interface timing diagram.
Pre-PWROK Metal VID
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 6). Once the ENABLE input exceeds the rising
threshold, the ISL62773 decodes and locks the decoded value
into an on-board hold register.
March 7, 2012
FN8263.0
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