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| 型号： | ISL6329CRZ |
| 厂商： | Intersil |
| 文件页数： | 16/38页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 60QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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ISL6329
TABLE 1. PRE-PWROK METAL VID CODES
OUTPUT VOLTAGE
SVI Mode
Once the controller has successfully soft-started and VDDPWRGD
SVC
0
0
1
1
SVD
0
1
0
1
(V)
1.1
1.0
0.9
0.8
transitions high, the Northbridge SVI interface can assert PWROK
to signal the ISL6329 to prepare for SVI commands. The
controller actively monitors the SVI interface for set VID
commands to move the plane voltages to start-up VID values.
Details of the SVI Bus protocol are provided in the AMD Design
Guide for Voltage Regulator Controllers Accepting Serial VID
Codes specification.
The Pre-PWROK metal VID code is decoded and latched on the
rising edge of the enable signal. Once enabled, the ISL6329
passes the Pre-PWROK metal VID code on to internal DAC
circuitry. The internal DAC circuitry begins to ramp both the VDD
and VDDNB planes to the decoded Pre-PWROK metal VID output
level. The digital soft-start circuitry actually stair steps the
internal reference to the target gradually over a fixed interval. The
controlled ramp of both output voltage planes reduces in-rush
current during the soft-start interval. At the end of the soft-start
interval, the VDDPWRGD output transitions high indicating both
output planes are within regulation limits.
Once the set VID command is received, the ISL6329 decodes the
information to determine which plane and the VID target
required. See Table 2. The internal DAC circuitry steps the
required output plane voltage to the new VID level. During this
time one or both of the planes could be targeted. In the event the
core voltage plane, VDD, is commanded to power off by serial VID
commands, the VDDPWRGD signal remains asserted. The
Northbridge voltage plane must remain active during this time.
If the PWROK input is de-asserted, then the controller steps both
VDD and VDDNB planes back to the stored Pre-PWROK metal VID
level in the holding register from initial soft-start. No attempt is
made to read the SVC and SVD inputs during this time. If PWROK
is reasserted, then the on-board SVI interface waits for a set VID
command.
1
2
3
4
5
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
VDD and VDDNB
metal_VID
V_SVI
metal_VID
V_SVI
VDDPWRGD
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
16
FN7800.0
April 19, 2011
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| ISL6329CRZ-T | 功能描述:电压模式 PWM 控制器 6+1 PHS DL PWM CONTRLR FOR CORE RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6329EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL6329 EVALUATION BOARD - 60 LEAD - QFN - ROHS COMPLIANT - Bulk |
| ISL6329IRZ | 功能描述:电压模式 PWM 控制器 6+1 PHS DL PWM CONTRLR FOR CORE RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6329IRZ-T | 功能描述:电压模式 PWM 控制器 6+1 PHS DL PWM CONTRLR FOR CORE RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6333ACRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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