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参数资料
| 型号： | ISL6329CRZ |
| 厂商： | Intersil |
| 文件页数： | 17/38页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 60QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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ISL6329
TABLE 2. SERIAL VID CODES
SVID[6:0]
000_0000b
000_0001b
000_0010b
000_0011b
000_0100b
000_0101b
000_0110b
000_0111b
000_1000b
000_1001b
000_1010b
000_1011b
000_1100b
000_1101b
000_1110b
000_1111b
001_0000b
001_0001b
001_0010b
001_0011b
001_0100b
001_0101b
001_0110b
001_0111b
001_1000b
001_1001b
001_1010b
001_1011b
001_1100b
001_1101b
001_1110b
001_1111b
VOLTAGE (V)
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
SVID[6:0]
010_0000b
010_0001b
010_0010b
010_0011b
010_0100b
010_0101b
010_0110b
010_0111b
010_1000b
010_1001b
010_1010b
010_1011b
010_1100b
010_1101b
010_1110b
010_1111b
011_0000b
011_0001b
011_0010b
011_0011b
011_0100b
011_0101b
011_0110b
011_0111b
011_1000b
011_1001b
011_1010b
011_1011b
011_1100b
011_1101b
011_1110b
011_1111b
VOLTAGE (V)
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
SVID[6:0]
100_0000b
100_0001b
100_0010b
100_0011b
100_0100b
100_0101b
100_0110b
100_0111b
100_1000b
100_1001b
100_1010b
100_1011b
100_1100b
100_1101b
100_1110b
100_1111b
101_0000b
101_0001b
101_0010b
101_0011b
101_0100b
101_0101b
101_0110b
101_0111b
101_1000b
101_1001b
101_1010b
101_1011b
101_1100b
101_1101b
101_1110b
101_1111b
VOLTAGE (V)
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875 *
0.4750 *
0.4625 *
0.4500 *
0.4375 *
0.4250 *
0.4125 *
0.4000 *
0.3875 *
0.3750 *
0.3625 *
SVID[6:0]
110_0000b
110_0001b
110_0010b
110_0011b
110_0100b
110_0101b
110_0110b
110_0111b
110_1000b
110_1001b
110_1010b
110_1011b
110_1100b
110_1101b
110_1110b
110_1111b
111_0000b
111_0001b
111_0010b
111_0011b
111_0100b
111_0101b
111_0110b
111_0111b
111_1000b
111_1001b
111_1010b
111_1011b
111_1100b
111_1101b
111_1110b
111_1111b
VOLTAGE (V)
0.3500 *
0.3375 *
0.3250 *
0.3125 *
0.3000 *
0.2875 *
0.2750 *
0.2625 *
0.2500 *
0.2375 *
0.2250 *
0.2125 *
0.2000 *
0.1875 *
0.1750 *
0.1625 *
0.1500 *
0.1375 *
0.1250 *
0.1125 *
0.1000 *
0.0875 *
0.0750 *
0.0625 *
0.0500 *
0.0375 *
0.0250 *
0.0125 *
OFF
OFF
OFF
OFF
NOTE:
* Indicates a VID not required for AMD Family 10h processors.
Power Savings Mode: PSI_L
Bit 7 of the Serial VID codes transmitted as part of the 8-bit data
stream over the SVI bus is allocated for the PSI_L. If bit 7 is 0,
then the processor is at an optimal load for the regulator to enter
power savings mode. If bit 7 is 1, then the regulator should not
be in power savings mode.
With the ISL6329, Power Savings mode is realized through
phase shedding, Gate Voltage Optimization and Diode
Emulation. Once a Serial VID command with Bit 7 set to 0 is
received, the ISL6329 will shed phases in a sequential manner
until then minimum phase count for PSI is reached. The
minimum phase count for PSI can be programmed via the FS pin
to be either 1 phase or 2 phases. If the FS resistor is tied to
ground, then the minimum phase count in PSI is 1 phase. If the
17
FS resistor is tied to VCC then the minimum phase count in PSI is
2 phases. Channels are shed in reverse sequential order so that
the highest numbered channel that is active will be shed first.
When a phase is shed, that phase will not go into a tri-state mode
until that phase would have had its PWM go HIGH.
When leaving Power Savings Mode, through the reception of a
Serial VID command with Bit 7 set to 1, the ISL6329 will
sequentially turn on phases starting with lowest numbered
inactive channel. When a phase is being reactivated, it will not
leave a tri-state until the PWM of that phase goes HIGH.
If, while in Power Savings Mode, a Serial VID command is
received that forces a VID level change while maintaining Bit 7 at
0, the ISL6329 will first exit the Power Savings Mode state as
described previously. The output voltage will then be stepped up
FN7800.0
April 19, 2011
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