参数资料
型号: ISL6329CRZ
厂商: Intersil
文件页数: 27/38页
文件大小: 0K
描述: IC CTRLR PWM SYNC BUCK DL 60QFN
标准包装: 43
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 0.0125 V ~ 1.55 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
ISL6329
TABLE 8. BITS [5:0] REGISTER RGS0 and RGS1 (VOLTAGE
MARGINING OFFSET) (Continued)
See Table 9 for a complete description of register RGS2 bits and
their functionality.
BIT5
VO5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT4
VO4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT3
VO3
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BIT2
VO2
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BIT1
VO1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BIT0
VO0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V OFFSET
(mV)
-25
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
Bits [7:6]
Bit 5
0
1
Bits [4:3]
00
01
10
11
Bits [2:1]
00
01
10
11
Bit 0
0
1
TABLE 9. BITS [7:0] REGISTER RGS2
Reserved
Offset Enable in Power Savings Mode
ENABLED (Default)
DISABLED
Number of PWM Cycles Between Dropping Phases
1 PWM Cycle (default)
2 PWM Cycles
4 PWM Cycles
0 PWM Cycles (All Phases Drop at Once)
Number of PWM Cycles Between Adding Phases
1 PWM Cycle (Default)
2 PWM Cycles
4 PWM Cycles
0 PWM Cycles (All Phases Added at Once)
Diode Emulation in Power Savings Mode
Disabled
Enabled (Default)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
400
425
450
475
500
525
550
Register RGS4 controls the number of active phases and the
GVOT level. It can only be written to when the PWROK signal is
low . Bit 7 is reserved. Bits 6 through 2 control the number of
active phases. It is important to note that is a bit is set to 1 then
all the lesser significant bits must also be set to 1 as well. Bits 1
and 0 control the GVOT voltage level. This register can only be
written to when PWROK is LOW.
TABLE 10. BITS [7:0] REGISTER RGS4
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
575
600
625
650
675
700
725
750
775
Bit 7
Bits [6:2]
00000
00001
00011
00111
01111
11111
Bits [1:0]
Reserved
Active Phase Control
Single Phase Regulator
Two Phase Regulator
Three Phase Regulator
Four Phase Regulator
Five Phase Regulator
Six Phase Regulator (Default)
GVOT Level
The bits for Register RGS2 control some of the functionality of
the ISL6329 for Power Savings Mode. Bit0 selects whether diode
emulation is enabled in Power Savings Mode. Bits 1 and 2
control the number of PWM cycles between adding of phases
when exiting Power Savings Mode. Bits 3 and 4 control the
number of PWM cycles between dropping of phases when
00
01
10
11
5.75V (Default)
6.75V
7.75V
11.2V
entering Power Savings Mode. Bit 5 will disable/enable the DAC
offset when in Power Savings Mode. Bits 6 and 7 are reserved.
27
The bits for Register RGS5 control some of the functionality of
the ISL6329 for Power Savings Mode, Droop Gain, NB Droop
FN7800.0
April 19, 2011
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