参数资料
型号: ISPPAC-POWR1208-01TN44I
厂商: Lattice Semiconductor Corporation
文件页数: 26/35页
文件大小: 0K
描述: IC ISP POWER MGR ANLG/LOG 44TQFP
标准包装: 160
系列: ispPAC®
应用: 电源监控器,序列发生器
输入电压: 0 V ~ 6 V
电源电压: 2.7 V ~ 5.5 V
电流 - 电源: 10mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 44-LQFP
供应商设备封装: 44-TQFP(10x10)
包装: 托盘
Lattice Semiconductor
ispPAC-POWR1208 Data Sheet
ADDCFG – This instruction is used to set the address of the CFG array for subsequent program or read operations.
This instruction also forces the outputs into the SAFESTATE.
DATACFG – This instruction is used to shift data into the CFG register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASECFG – This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
PROGCFG – This instruction programs the selected CFG array column. This speci?c column is preselected by
using ADDCFG instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG
state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces
the outputs into the SAFESTATE.
READCFG – This instruction is used to read the content of the selected CFG array column. This speci?c column is
preselected by using ADDCFG instruction. This instruction also forces the outputs into the SAFESTATE.
CFGBE – This instruction will bulk erase all E 2 CMOS bits (CFG, PLD, UES, and ESF) in the ispPAC-POWR1208.
The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the out-
puts into the SAFESTATE.
SAFESTATE – This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET
drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG
state.
PROGRAMEN – This instruction enables the programming mode of the ispPAC-POWR1208. This instruction also
forces the outputs into the SAFESTATE.
IDCODE – This instruction connects the output of the Identi?cation Code Data Shift (IDCODE) Register to TDO
(Figure 1-13), to support reading out the identi?cation code.
Figure 1-13. IDCODE Register
TDO
Bit
31
Bit
30
Bit
29
Bit
28
Bit
27
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
PROGRAMDIS – This instruction disables the programming mode of the ispPAC-POWR1208. The Test-Logic-
Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR1208.
ADDSTATUS – This instruction is used to both connect the status register to TDO (Figure 1-14) and latch the 12
voltage monitor (comparator outputs) into the status register. Latching of the 12 comparator outputs into the status
register occurs during Capture-Data-Register JTAG state.
Figure 1-14. Status Register
TDO
VMON
1
VMON
2
VMON
3
VMON
4
VMON
5
VMON
6
VMON
7
VMON
8
VMON
9
VMON
10
VMON
11
VMON
12
ERASEUES – This instruction will bulk erase the content of the UES E 2 CMOS memory. The device must already
be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE.
SHIFTUES – This instruction both reads the E 2 CMOS bits into the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure U), to support programming or reading of the user electronic
signature bits.
1-25
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