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| 型号： | KIT33982CEVBE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 10/36页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 33982 HIGH SIDE SWITCH |
| 标准包装： | 1 |
| 主要目的： | 电源管理，高端驱动器（内部 FET） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33982 |
| 主要属性： | 输出电流监控，2 个 SPI 可选电流比 |
| 次要属性： | 过电流限制SPI控制，开路负载侦测，输出开/关，转换速率 |
| 已供物品： | 板，CD |
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ? V DD ? 5.5 V, 6.0 V ? V PWR ? 27 V, -40 ? C ? T A ? 125 ? C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T A = 25 ? C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (CONTINUED)
Output Negative Clamp Voltage
V CL
V
0.5 A < I HS < 2.0 A, Output OFF
- 20
–
-15
Over-temperature Shutdown (13)
Over-temperature Shutdown Hysteresis (13)
T SD
T SD(HYS)
160
5.0
175
–
190
20
? C
? C
CONTROL INTERFACE
Input Logic High-voltage (14)
V IH
0.7 x V DD
–
–
V
Input Logic Low-voltage
V IL
–
–
0.2 x
V DD
V
Input Logic Voltage Hysteresis (15)
Input Logic Pull-down Current (SCLK, IN, SI)
RST Input Voltage Range
V IN(HYS)
I DWN
V RST
100
5.0
4.5
600
–
5.0
1200
20
5.5
mV
? A
V
SO, FS Tri-state Capacitance
C SO
–
–
20
pF
Input Logic Pull-down Resistor (RST) and WAKE
Input Capacitance (16)
R DWN
C IN
100
–
200
4.0
400
12
k ?
pF
WAKE Input Clamp Voltage (17)
V CL(WAKE)
V
I CL(WAKE) < 2.5 mA
WAKE Input Forward Voltage
I CL(WAKE) = -2.5 mA
SO High-state Output Voltage
I OH = 1.0 mA
FS, SO Low-state Output Voltage
I OL = -1.6 mA
SO Tri-state Leakage Current
CS > 0.7 x V DD
V F(WAKE)
V SOH
V SOL
I SO(LEAK)
7.0
- 2.0
0.8 x V DD
–
-5.0
–
–
–
0.2
0.0
14
-0.3
–
0.4
5.0
V
V
V
? A
Input Logic Pull-up Current
I UP
? A
CS, V IN > 0.7 x V DD
FSI Input Pin External Pull-down Resistance
R FS
5.0
–
20
k ?
FSI Disabled, HS Indeterminate
FSI Enabled, HS OFF
FSI Enabled, HS ON
R FSDIS
R FSOFF
R FSON
–
6.0
30
0.0
10
–
1.0
14
–
Notes
13. Guaranteed by process monitoring. Not production tested.
14. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage reference to V PWR .
15.
16.
17.
18.
No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested.
Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
The current must be limited by a series resistance when using voltages > 7.0 V.
Pull-up current is with CS OPEN. CS has an active internal pull-up to V DD .
33982
Analog Integrated Circuit Device Data ?
10
Freescale Semiconductor
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