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参数资料
| 型号： | KIT33982CEVBE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 24/36页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 33982 HIGH SIDE SWITCH |
| 标准包装： | 1 |
| 主要目的： | 电源管理，高端驱动器（内部 FET） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33982 |
| 主要属性： | 输出电流监控，2 个 SPI 可选电流比 |
| 次要属性： | 过电流限制SPI控制，开路负载侦测，输出开/关，转换速率 |
| 已供物品： | 板，CD |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 10. Serial Input Address and Configuration Bit
Map
eight possible levels as defined in Table 11 . Bit D3 is used to
set the over-current high detection level to one of two levels
SI
Register
D7 D6 D5 D4
Serial Input Data
D3 D2
D1
D0
Table 11. Over-current Low Detection Levels
SOCL2 SOCL1 SOCL0 Over-current Low Detection
STATR
x
0
0
0
0
SOA2
SOA1
SOA0
(D2)
(D1)
(D0)
(Amperes)
OCR
SOCHLR
CDTOLR
DICR
x
x
x
x
0
0
0
1
0
1
1
0
1
0
1
0
0 0
SOCH SOCL2
OL_dis CD_dis
FAST CSNS
SR high
CSNS
EN
SOCL1
OCLT1
IN dis
IN_SPI
SOCL0
OCLT0
A/O
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
50
45
40
35
30
OSDR
WDR
NAR
0
1
0
1
1
1
0
0
1
1
1
0
0
0
0
OSD2
0
0
OSD1
WD1
0
OSD0
WD0
0
1
1
1
0
1
1
1
0
1
25
20
15
UOVR
1
1
1
0
0
0
UV_dis
OV_dis
?
TEST
x
1
1
1
Freescale Internal Use (Test)
Table 12. Over-current High Detection Levels
x = Don’t care.
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses and their impact on device operation.
SOCH (D3)
0
1
Over-current High Detection
(Amperes)
150
100
Address x000 — Status Register (STATR)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2, D1, and D0 determine the content of the first eight bits of
SO data. In addition to the device status, this feature provides
the ability to read the content of the OCR, SOCHLR,
CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers.
Address x001 — Output Control Register (OCR)
Address x011 — Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an over-current low
condition before output latches OFF occurs. Bits D1 and D0
allow the MCU to select one of four fault blanking times
defined in Table 13 . Note that these timeouts apply only to
the over-current low detection levels. If the selected over-
current high level is reached, the device will latch off within
20 ? s .
Table 13. Over-current Low Detection Blanking Time
The OCR register allows the MCU to control the output
through the SPI. Incoming message bit D0 (IN_SPI) reflects
the desired states of the high-side output: a Logic [1] enables
the output switch and a Logic [0] turns it OFF. A Logic [1] on
message bit D1 enables the Current Sense (CSNS) pin. Bits
D2 and D3 must be Logic [0]. Bit D7 is used to feed the
watchdog if enabled.
OCLT [1:0]
00
01
10
11
Timing
155 ms
10 ms
1.2 ms
150 ? s
Address x010 — Select Over-current High and Low
Register (SOCHLR)
The SOCHLR register allows the MCU to configure the
output over-current low and high detection levels,
respectively. In addition to protecting the device, this slow
blow fuse emulation feature can be used to optimize the load
requirements to match system characteristics. Bits D2 : D0
are used to set the over-current low detection level to one of
A Logic [1] on bit D2 disables the over-current low
(CD_dis) detection timeout feature. A Logic [1] on bit D3
disables the open load (OL) detection feature.
Address x100 — Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable,
or configure the direct IN pin control of the output. A Logic [0]
on bit D1 will enable the output for direct control by the IN pin.
A Logic [1] on bit D1 will disable the output from direct control.
33982
Analog Integrated Circuit Device Data ?
24
Freescale Semiconductor
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