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| 型号： | KIT33982CEVBE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 32/36页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 33982 HIGH SIDE SWITCH |
| 标准包装： | 1 |
| 主要目的： | 电源管理，高端驱动器（内部 FET） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33982 |
| 主要属性： | 输出电流监控，2 个 SPI 可选电流比 |
| 次要属性： | 过电流限制SPI控制，开路负载侦测，输出开/关，转换速率 |
| 已供物品： | 板，CD |
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ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 4.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 4.0)
Introduction
This thermal addendum is provided as a supplement to the 33982 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
Packaging and Thermal Considerations
This package is a dual die package. There are two heat sources in the package
independently heating with P 1 and P 2 . This results in two junction temperatures,
T J1 and T J2 , and a thermal resistance matrix with R ? JA mn .
For m , n = 1, R ? JA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P 1 .
For m = 1, n = 2, R ? JA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P 2 . This applies to R ? J21
and R ? J22 , respectively.
33982
High Side Switch
98ARL10521D
16-PIN PQFN
12 mm x 12 mm
Note For package dimensions, refer to
T J1
T J2
=
R ? JA11
R ? JA21
R ? JA12
R ? JA22
.
P 1
P 2
98ARL10521D.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below.
Standards
Table 19. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [ ? C/W]
Thermal
Resistance
m = 1,
m = 1, n = 2
m = 2,
n =1
m = 2, n = 1
n =2
1.0
R ? JA mn (1) , (2)
20
16
39
0.2
R ? JB mn
6
2.0
26
1.0
<0.5
0.0
1.0
R ? JC mn
R ? JA mn (1) , (4) 53 40 73
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and ?
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
0.2
* All measurements ?
are in millimeters
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
Figure 13. Surface Mount for Power PQFN
with Exposed Pads
33982
Analog Integrated Circuit Device Data ?
32
Freescale Semiconductor
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| KIT33988CEVBE | 功能描述:电源管理IC开发工具 HIGH SIDE SWITCH (8.0M) RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| KIT33989DWEVB | 功能描述:界面开发工具 33989DW HS SBC EVAL KIT RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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