参数资料
型号: KIT33982CEVBE
厂商: Freescale Semiconductor
文件页数: 13/36页
文件大小: 0K
描述: KIT EVAL 33982 HIGH SIDE SWITCH
标准包装: 1
主要目的: 电源管理,高端驱动器(内部 FET)
嵌入式:
已用 IC / 零件: MC33982
主要属性: 输出电流监控,2 个 SPI 可选电流比
次要属性: 过电流限制SPI控制,开路负载侦测,输出开/关,转换速率
已供物品: 板,CD
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ? V DD ? 5.5 V, 6.0 V ? V PWR ? 27 V, -40 ? C ? T A ? 125 ? C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T A = 25 ? C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (26)
t CS
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup
Time) (26)
t ENBL
5.0
? s
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Required High-state Duration of SCLK (Required Setup Time) (26)
t LEAD
t WSCLKH
50
167
167
ns
ns
Required Low-state Duration of SCLK (Required Setup Time)
t WSCLKL
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (26)
t LAG
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)
t SI(SU)
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time) (27)
t SI(HOLD)
25
83
ns
SO Rise Time
t RSO
ns
C L = 200 pF
SO Fall Time
C L = 200 pF
t FSO
25
25
50
50
ns
SI, CS, SCLK, Incoming Signal Rise Time (27)
t RSI
50
ns
SI, CS, SCLK, Incoming Signal Fall
Time (27)
t FSI
50
ns
Time from Falling Edge of CS to SO
Time from Rising Edge of CS to SO
Low-impedance (28)
High-impedance (29)
t SO(EN)
t SO(DIS)
65
145
145
ns
ns
Time from Rising Edge of SCLK to SO Data Valid (30)
t VALID
ns
0.2 V DD ? ? SO ? 0.8 V DD , C L = 200 pF
65
105
Notes
26.
27.
28.
29.
30.
Maximum setup time required for th e 33982 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS , and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 k ?? on pull-up on CS .
Time required for output status data to be terminated at SO. 1.0 k ?? on pull-up on CS .
Time required to obtain valid data out from SO following the rise of SCLK.
33982
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
13
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