参数资料
型号: KMPC8360EZUAJDG
厂商: Freescale Semiconductor
文件页数: 54/95页
文件大小: 0K
描述: IC MPU PWRQUICC II 740-TBGA
标准包装: 2
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
电压: 1.2V
安装类型: 表面贴装
封装/外壳: 740-LBGA
供应商设备封装: 740-TBGA(37.5x37.5)
包装: 托盘
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
58
Freescale Semiconductor
TDM/SI
17.2
TDM/SI AC Timing Specifications
Table 57 provides the TDM/SI input and output AC timing specifications.
Figure 43 provides the AC test load for the TDM/SI.
Figure 43. TDM/SI AC Test Load
Figure 44 represents the AC timing from Table 55. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ OVDD
—±10
μA
Table 57. TDM/SI AC Timing Specifications1
Characteristic
Symbol2
Min
Max3
Unit
TDM/SI outputs—External clock delay
tSEKHOV
210
ns
TDM/SI outputs—External clock high impedance
tSEKHOX
210
ns
TDM/SI inputs—External clock input setup time
tSEIVKH
5—
ns
TDM/SI inputs—External clock input hold time
tSEIXKH
2—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI
outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and SITXCEI[TXCEIx]. See
the
MPC8360E Integrated Communications Processor Family Reference Manual for more details.
Table 56. TDM/SI DC Electrical Characteristics (continued)
Characteristic
Symbol
Condition
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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