参数资料
型号: KSZ8842-PMQL-EVAL
厂商: Micrel Inc
文件页数: 26/119页
文件大小: 0K
描述: BOARD EVALUATION KSZ8842-PMQL
标准包装: 1
主要目的: 接口,以太网控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要属性: 2 个端口,100BASE-TX/10BASE-T
次要属性: 8/16 位接口,LinkMD 线缆诊断
已供物品:
产品目录页面: 1114 (CN2011-ZH PDF)
相关产品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名称: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
14
M9999-100207-1.5
Pin
Number
Pin
Name
Type
Pin Function
71
TRDYN
I/O
PCI Target Ready
As a bus target, this signal is asserted low to indicate valid data phases on PAD [31:0]
during read data phases, indicating it is ready to accept data during write data phases.
As a master, it will monitor this TRDYN signal that indicates the target is ready for data
during read/write operation.
72
STOPN
I/O
PCI Stop
This signal is asserted low by the target device to stop the current transaction.
73
IDSEL
I/O
PCI Initialization Device Select
This signal is used to select the KSZ8842-PMQL during configuration read and write
transactions.
74
DEVSELN
I/O
PCI Device Select
This signal is asserted low when it is selected as a target during a bus transaction. As a
bus master, the KSZ8842-PMQL samples this signal to insure that the destination
address for the data transfer is recognized by a PCI target.
75
REQN
O
PCI Bus Request
The KSZ8842-PMQL will assert this signal low to request PCI bus master operation.
76
GNTN
I
PCI Bus Grant
This signal is asserted low to indicate to the KSZ8842-PMQL that it has been granted
the PCI bus master operation.
77
PERRN
I/O
PCI Parity Error
The KSZ8842-PMQL as a master or target will assert this signal low to indicate a parity
error on any incoming data. As a bus master, it will monitor this signal on all write
operations.
78
DGND
Gnd
Digital I/O ground
79
VDDIO
P
3.3V digital I/O VDD
80
SERRN
O
PCI System Error
This system error signal is asserted low by the KSZ8842-PMQL.This signal is used to
report address parity errors.
81
NC
No connect
82
NC
No connect
83
NC
No connect
84
NC
No connect
85
CBE3N
I
86
CBE2N
I
87
CBE1N
I
88
CBE0N
I
Command and Byte Enable
These signals are multiplexed on the same PCI pins. During the address phase, these
lines define the bus command. During the data phase, these lines are used as Byte
Enables. The Byte enables are valid for the entire data phase and determine which byte
lanes carry meaningful data.
89
PAD31
I/O
PCI Address / Data 31
Address and data are multiplexed on the all of the PAD pins. The PAD pins carry the
physical address during the first clock cycle of a transaction, and carry data during the
subsequent clock cycles.
90
DGND
Gnd
Digital core ground
91
VDDC
P
1.2V digital core VDD
92
VDDIO
P
3.3V digital I/O VDD
93
PAD30
I/O
PCI Address / Data 30
94
PAD29
I/O
PCI Address / Data 29
95
PAD28
I/O
PCI Address / Data 28
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