参数资料
型号: KSZ8842-PMQL-EVAL
厂商: Micrel Inc
文件页数: 63/119页
文件大小: 0K
描述: BOARD EVALUATION KSZ8842-PMQL
标准包装: 1
主要目的: 接口,以太网控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要属性: 2 个端口,100BASE-TX/10BASE-T
次要属性: 8/16 位接口,LinkMD 线缆诊断
已供物品:
产品目录页面: 1114 (CN2011-ZH PDF)
相关产品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名称: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
48
M9999-100207-1.5
Bit
Default
R/W
Description
25
0
RW
DMRPSIE DMA MAC Receive Process Stopped Interrupt Enable
When this bit is set, the DMA MAC Receive Process Stopped Interrupt is
enabled.
When this bit is reset, the DMA MAC Receive Process Stopped Interrupt
is disabled.
24 – 0
RO
Reserved
Interrupt Status Register (INTST Offset 0x002C)
This register contains the status bits for the CPU. When the corresponding bit is set, the CPU is interrupted. The driver
usually reads this register during interrupt service routine or polling. The register bits are not cleared when read. Each
field can be masked.
The following table shows the register bit fields.
Bit
Default
R/W
Description
31
0
RW
DMLCS DMA MAC Link Changed Status
When this bit is set, it indicates that the DMA MAC link status has
changed from link up to link down or from link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
30
0
RW
DMTS DMA MAC Transmit Status
When this bit is set, it indicates that the DMA MAC has transmitted at
least a frame on the DMA port and the MAC is ready for new frames from
the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
29
0
RW
DMRS DMA MAC Receive Status
When this bit is set, it indicates that the DMA MAC has received a frame
from the DMA port and it is ready for the host to process
This edge-triggered interrupt status is cleared by writing 1 to this bit.
28
0
RW
DMTBUS DMA MAC Transmit Buffer Unavailable Status
When this bit is set, it indicates that the next descriptor on the transmit list
is owned by the host and cannot be acquired by the KSZ8842-
PMQL/PMBL. The transmission process is suspended. To resume
processing transmit descriptors, the host should change the ownership bit
of the descriptor and then issue a transmit start command.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
27
0
RW
DMRBUS DMA MAC Receive Buffer Unavailable Status
When this bit is set, it indicates that the descriptor list is owned by the host
and cannot be acquired by the KSZ8842-PMQL/PMBL. The receiving
process is suspended. To resume processing receive descriptors, the
host should change the ownership of the descriptor and may issue a
receive start command. If no receive start command is issued, the
receiving process resumes when the next recognized incoming frame is
received. After the first assertion, this bit is not asserted for any
subsequent not owned receive descriptors fetches. This bit is asserted
only when the previous receive descriptor was owned by the KSZ8842-
PMQL/PMBL.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
26
0
RW
DMTPSS DMA MAC Transmit Process Stopped Status
Asserted when the DMA MAC transmit process enters the stopped state.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
25
0
RW
DMRPSS DMA MAC Receive Process Stopped Status
Asserted when the DMA MAC receive process enters the stopped state.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
24 – 0
RO
Reserved
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