参数资料
型号: KSZ8842-PMQL-EVAL
厂商: Micrel Inc
文件页数: 8/119页
文件大小: 0K
描述: BOARD EVALUATION KSZ8842-PMQL
标准包装: 1
主要目的: 接口,以太网控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要属性: 2 个端口,100BASE-TX/10BASE-T
次要属性: 8/16 位接口,LinkMD 线缆诊断
已供物品:
产品目录页面: 1114 (CN2011-ZH PDF)
相关产品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名称: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
105
M9999-100207-1.5
Examples:
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to reg. IACR with 0x1c0e (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 =1, there was a counter overflow
// If bit 30 =0, restart (reread) from this register
Read reg. IADR4 (MIB counter value 15-0)
2. MIB Counter Read (read port 2 “Rx64Octets” counter at indirect address offset 0x2E)
Write to reg. IACR with 0x1c2e (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 =1, there was a counter overflow
// If bit 30 =0, restart (reread) from this register
Read reg. IADR4 (MIB counter value 15-0)
3. MIB Counter Read (read “Port1 TX Drop Packets” counter at indirect address offset 0x100)
Write to reg. IACR with 0x1d00 (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR4 (MIB counter value 15-0)
Additional MIB Information
Per Port MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
All Port Dropped Packet MIB counters are not cleared after they are accessed. The application needs to keep track of
overflow and valid conditions on these counters.
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相关代理商/技术参数
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