参数资料
型号: KSZ8842-PMQL-EVAL
厂商: Micrel Inc
文件页数: 55/119页
文件大小: 0K
描述: BOARD EVALUATION KSZ8842-PMQL
标准包装: 1
主要目的: 接口,以太网控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要属性: 2 个端口,100BASE-TX/10BASE-T
次要属性: 8/16 位接口,LinkMD 线缆诊断
已供物品:
产品目录页面: 1114 (CN2011-ZH PDF)
相关产品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名称: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
40
M9999-100207-1.5
The following table describes the CFCS register bit fields.
Bit
Type
Default
Description
31
Status
0
Detected Parity Error
When set, indicates that the KSZ8842-PMQL/PMBL detected a
parity error, even if parity error handling is disabled in parity error
response (CFCS[6]).
30
Status
0
Signal System Error
When set, indicates that the KSZ8842-PMQL/PMBL asserted the
system error SERR_N pin/ball.
29
Status
0
Received Master Abort
When set, indicates that the KSZ8842-PMQL/PMBL terminated a
master transaction with master abort.
28
Status
0
Received Target Abort
When set, indicates that the KSZ8842-PMQL/PMBL master
transaction was terminated due to a target abort.
27
Status
0
Target Abort
This bit is set by KSZ8842-PMQL/PMBL whenever it terminates
with a Target Abort. The CSR registers are all 32-bit Little Endian
format.
For PCI register Read cycles, the KSZ8842-PMQL/PMBL allows
any different combination of CBEN. For PCI register bus cycles,
only byte, word (16-bit), or Dword (32-bit) accesses are allowed.
Any other combination is illegal and is target aborted.
26 – 25
Status
01
Device Select Timing
Indicates the timing of the assertion of device select(DEVSEL_N).
These bits are fixed at 01, which indicates a middle assertion of
DEVSEL_N.
24
Status
0
Data Parity Report
This bit is set when the following conditions are met:
The KSZ8842-PMQL/PMBL asserts parity error PERR_N or it
senses the assertion of PERR_N by another device.
The KSZ8842-PMQL/PMBL operates as a bus master for the
operation that caused the error.
Parity error response (CFCS[6]) is set.
23 – 22
Reserved
00
Reserved
21
Status
0
66MHz Capable
0 = Not 66MHz capable
20 – 9
Reserved
0x000
Reserved
8
Command
0
System Error Enable
When set, the KSZ8842-PMQL/PMBL asserts system error
(SERR_N) when it detects a parity error on the address phase.
7
Reserved
0
Reserved
6
Command
0
Parity Error Response
When set, the KSZ8842-PMQL/PMBL asserts fatal bus error after it
detects a parity error.
When reset, any detected parity error is ignored and the KSZ8842-
PMQL/PMBL continues normal operation. Parity checking is
disabled after hardware reset.
5 – 3
Reserved
000
Reserved
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