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参数资料
| 型号： | LC5768VG-10F484I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 10 ns, PBGA484 |
| 封装： | FBGA-484 |
| 文件页数： | 3/48页 |
| 文件大小： | 237K |
| 代理商： | LC5768VG-10F484I |
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Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
11
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 5000VG devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for verication. In addition, these devices
can be linked into a board-level serial scan path for more board-level testing. The test access port has its own sup-
ply voltage and can operate with LVCMOS3.3, 2.5 and 1.8V standards.
sysIO Quick Conguration
To facilitate the most efcient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for conguration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 5000VG family of devices
allows this by offering the user the ability to quickly congure the physical nature of the sysIO cells. This quick con-
guration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lat-
tice's ispVM System programming software can either perform the quick conguration through the PC parallel
port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
In-system programming of devices provides a number of signicant benets including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-eld modications. All ispMACH 5000VG devices provide
In-System Programming (ISP
TM) capability through their Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE
1532 as the communication interface through which ISP is achieved, customers get the benet of a standard, well-
dened interface.
The ispMACH 5000VG devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispMACH 5000VG devices. The software takes the
JEDEC le output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output les in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispMACH 5000VG devices during the testing
of a circuit board.
Security Bit
A programmable security bit is provided on the ispMACH 5000VG devices as a deterrent to unauthorized copying
of the array conguration patterns. Once programmed, this bit prevents readback of the programmed pattern by a
device programmer, securing proprietary design from competitors. The security bit also prevents programming and
verication. The entire device must be erased in order to erase the security bit.
Hot Socketing
The ispMACH 5000VG devices are well suited for those applications that require hot socketing capability. Hot sock-
eting a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs with-
out being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active
signals.
Density Migration
The ispMACH 5000 family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high density device to a lower density device. However, the exact details of the nal resource utilization
will impact the likely success in each case.
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| LC51024VG-10F484C | |
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| LC5768VG-12F256I | |
| LC5512B-75F256C | |
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相关代理商/技术参数 |
参数描述 |
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| LC5768VG-12F256I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5768VG-12F484I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5768VG-5F256C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5768VG-5F484C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5768VG-5FN484C | 制造商:Lattice Semiconductor Corporation 功能描述:CPLD ispMACH 5000VG Family 768 Macro Cells 178.6MHz 3.3V 484-Pin FBGA |
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