- 您现在的位置：买卖IC网 > PDF目录2082 > LMK04010BISQ/NOPB (National Semiconductor)IC CLOCK CONDITIONER W/PLL 48LLP PDF资料下载
参数资料
| 型号： | LMK04010BISQ/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 19/65页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CONDITIONER W/PLL 48LLP |
| 标准包装： | 1,000 |
| 系列： | PowerWise® |
| 类型： | 时钟调节器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | 2VPECL，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.296GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-LLP（7x7） |
| 包装： | 带卷 (TR) |
| 其它名称： | LMK04010BISQ |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
The Phase Frequency Detector in PLL2 then compares the divided (R Divider 2) reference signal from the PLL2
OSCin port with the divided (N Divider 2 and VCO Divider) output of the internal VCO. The bandwidth of the
external loop filter for PLL2 should be designed to be wide enough to take advantage of the low in-band phase
noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is passed through a
common VCO divider block and placed on a distribution path for the clock distribution section. It is also routed to
the PLL2_N counter. Each clock output channel allows the user to select a path with a programmable divider
block, a phase synchronization circuit, a programmable delay, and LVDS/LVPECL/2VPECL/LVCMOS compatible
output buffers.
Phase Detector 1 (PD1)
Phase Detector 1 in PLL1 (PD1) can operate up to 40 MHz. Since a narrow loop bandwidth should be used for
PLL1, the need to operate at high phase detector rate to lower the in-band phase noise becomes unnecessary.
Phase Detector 2 (PD2)
Phase Detector 2 in PLL2 (PD2) supports a maximum comparison rate of 100 MHz, though the actual maximum
frequency at the input port (PLL2 OSCin/OSCin*) is 250 MHz. Operating at highest possible phase detector rate
will ensure low in-band phase noise for PLL2 which in turn produces lower total jitter, as the in-band phase noise
from the reference input and PLL are proportional to N2.
PLL2 Frequency Doubler
The PLL2 reference input at the OSCin port may be optionally routed through a frequency doubler function rather
than through the PLL2_R counter. The maximum phase comparison frequency of the PLL2 phase detector is 100
MHz, so the input to the frequency doubler is limited to a maximum of 50 MHz. The frequency doubler feature
allows the phase comparison frequency to be increased when a relative low frequency oscillator is driving the
OSCin port. By doubling the PLL2 phase comparison frequency, the in-band PLL2 noise is reduced by about 3
dB.
Inputs / Outputs
PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*)
The reference clock inputs for PLL1 may be selected from either CLKin0 and CLKin1. The user has the capability
to manually select one of the two inputs or to configure an automatic switching mode operation. A detailed
description of this function is described in the uWire programming section of this data sheet.
PLL2 OSCin / OSCin* Port
The feedback from the external oscillator being locked with PLL1 is injected to the PLL2 OSCin/OSCin* pins.
This input may be driven with either a single- ended or differential signal. If operated in single ended mode, the
unused input should be tied to GND with a 0.1 F capacitor. Either AC or DC coupling is acceptable. Internal to
the chip, this signal is routed to the PLL1_N Counter and to the reference input for PLL2. The internal circuitry of
the OSCin port also supports the optional implementation of a crystal based oscillator circuit. A crystal, varactor
diode and a small number of other external components may be used to implement the oscillator. The internal
oscillator circuit is enabled by setting the EN_PLL2_XTAL bit.
CPout1 / CPout2
The CPout1 pin provides the charge pump current output to drive the loop filter for PLL1. This loop filter should
be configured so that the total loop bandwidth for PLL1 is less than 200 Hz. When combined with an external
oscillator that has low phase noise at offsets close to the carrier, PLL1 generates a reference for PLL2 that is
frequency locked to the PLL1 reference clock but has the phase noise performance of the oscillator. The CPout2
pin provides the charge pump current output to drive the loop filter for PLL2. This loop filter should be configured
so that the total loop bandwidth for PLL2 is in the range of 50 kHz to 200 kHz. See the section on uWire device
control for a description of the charge pump current gain control.
26
Copyright 2008–2011, Texas Instruments Incorporated
相关PDF资料 |
PDF描述 |
|---|---|
| LMV393MUTAG | IC OP AMP DUAL GP LV LV 8-UDFN |
| LMX339HASD+T | IC COMPARATOR GP QUAD 14-SOIC |
| LT1011AIS8#TRPBF | IC VOLTAGE COMPARATOR 5V 8-SOIC |
| LT1016IS8#TRPBF | IC COMPARATOR 10NS HI-SPD 8-SOIC |
| LT1017IS8#TRPBF | IC COMPARATOR MICRPWR DUAL 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LMK04010BISQX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04010BISQX/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LMK04011BISQ | 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R |
| LMK04011BISQ/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LMK04011BISQE | 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R 制造商:Texas Instruments 功能描述:PRECISION CLOCK CONDITIONER, 48LLP |
发布紧急采购，3分钟左右您将得到回复。