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参数资料
| 型号： | M38B79FFFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 4/112页 |
| 文件大小： | 1862K |
| 代理商： | M38B79FFFP |
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98
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The instruction with the addressing mode which uses the value
of a direction register as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before
executing serial I/O transfer and serial I/O automatic transfer.
Automatic Transfer Serial I/O
When using the automatic transfer serial I/O mode of the serial I/
O1, set an automatic transfer interval as the following.
Otherwise the serial data might be incorrectly transmitted/re-
ceived.
Set an automatic transfer interval for each 1-byte data transfer as
the following:
(1) Not using FLD controller
Keep the interval for 5 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for 17 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(b) Using gradation display
Keep the interval for 27 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC
≥ 4.0 V
is recommended. When a D-A converter is not used, set the value
of D-A conversion register to “0016”.
Instruction Execution Time
The instruction execution time is obtained by multiplying the pe-
riod of the internal clock
φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock
φ is half of the XIN period in high-
speed mode.
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