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参数资料
型号： M38B79FFFP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 4.2 MHz, MICROCONTROLLER, PQFP100
封装： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件页数： 61/112页
文件大小： 1862K
代理商： M38B79FFFP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
49
Fig. 49 Segment/Digit setting example
FLD Automatic Display Pins
P0 to P6 are the pins capable of automatic display output for the
FLD. The FLD starts operating by setting the automatic display
control bit (bit 0 at address 0EF416) to “1”. There is the FLD output
function that outputs the RAM contents from the port every timing
or the digit output function that drives the port high with a digit tim-
Setting method
The individual bits of the digit output set switch registers (addresses 0EF216, 0EF316) can
set each pin to either an FLD port (“0”) or a digit port (“1”).
When the pins are set for the digit port, the digit pulse output function is enabled, so that the
digit pulses can always be output regardless the value of FLD automatic display RAM.
Setting the automatic display control bit (bit 0 of address 0EF416) to “1” can set these ports
to the FLD exclusive use port.
The individual bits of the FLD/Port switch register (addresses 0EF916 to 0EFB16) can set
each pin to either an FLD port (“1”) or a general-purpose port (“0”).
The individual bits of the port P6 FLD/Port switch register (address 0EFB16) can set each
pin to either FLD port (“1”) or general-purpose port (“0”). A variety of output pulses can be
available by setting of the FLD output control register (address 0EFC16). The port output
structure is the CMOS output. When using the port as a display pin, a driver IC must be in-
stalled externally.
ing. The FLD can be displayed using the FLD output for the seg-
ments and the digit or FLD output for the digits. When using the
FLD output for the digits, be sure to write digit display patterns to
the RAM in advance. The remaining segment and digit lines can
be used as general-purpose ports. Settings of each port are
shown below.
Table 10 Pins in FLD automatic display mode
Port
P0, P2
Automatic display pin
FLD0 to FLD15
P1, P3
FLD16 to FLD31
P4, P5,
P60 to P63
P64 to P67
FLD32 to FLD51
FLD52 to FLD55
Port P0
Port P1
Number of segments
Number of digits
Port P2
36
16
Port P3
Setting example 1
This is a register setup example where only FLD output is used.
In this case, the digit display output pattern must be set in the FLD automatic
display RAM in advance.
1
FLD32 (SEG output)
FLD33 (SEG output)
FLD34 (SEG output)
FLD35 (SEG output)
FLD36 (SEG output)
FLD37 (SEG output)
FLD38 (SEG output)
FLD39(SEG output)
FLD16 (SEG output)
FLD17 (SEG output)
FLD18 (SEG output)
FLD19 (SEG output)
FLD20 (SEG output)
FLD21 (SEG output)
FLD22 (SEG output)
FLD23 (SEG output)
FLD0 (DIG output)
FLD1 (DIG output)
FLD2 (DIG output)
FLD3 (DIG output)
FLD4 (DIG output)
FLD5 (DIG output)
FLD6 (DIG output)
FLD7 (DIG output)
0
FLD8 (DIG output)
FLD9 (DIG output)
FLD10 (DIG output)
FLD11 (DIG output)
FLD12 (DIG output)
FLD13 (DIG output)
FLD14 (DIG output)
FLD15 (DIG output)
0
FLD24 (SEG output)
FLD25 (SEG output)
FLD26 (SEG output)
FLD27 (SEG output)
FLD28 (SEG output)
FLD29 (SEG output)
FLD30 (SEG output)
FLD31 (SEG output)
Port P4
1
FLD40 (SEG output)
FLD41 (SEG output)
FLD42 (SEG output)
FLD43 (SEG output)
FLD44 (SEG output)
FLD45 (SEG output)
FLD46 (SEG output)
FLD47 (SEG output)
Port P5
1
0
FLD48 (SEG output)
FLD49 (SEG output)
FLD50 (SEG output)
FLD51 (SEG output)
FLD52 (port output)
FLD53 (port output)
FLD54 (port output)
FLD55 (port output)
Port P6
Port P0
Port P1
Port P2
28
12
Port P3
Setting example 2
This is a register setup example where both FLD output and digit waveform output are
used. In this case, because the digit display output is automatically generated, there is
no need to set the display pattern in the FLD automatic display RAM.
1
FLD32 (SEG output)
FLD33 (SEG output)
FLD34 (SEG output)
FLD35 (SEG output)
FLD36 (SEG output)
FLD37 (SEG output)
FLD38 (SEG output)
FLD39 (SEG output)
FLD16 (SEG output)
FLD17 (SEG output)
FLD18 (SEG output)
FLD19 (SEG output)
FLD20 (SEG output)
FLD21 (SEG output)
FLD22 (SEG output)
FLD23 (SEG output)
FLD0 (DIG output)
FLD1 (DIG output)
FLD2 (DIG output)
FLD3 (DIG output)
FLD4 (DIG output)
FLD5 (DIG output)
FLD6 (DIG output)
FLD7 (DIG output)
1
FLD8 (DIG output)
FLD9 (DIG output)
FLD10 (DIG output)
FLD11 (DIG output)
FLD12 (SEG output)
FLD13 (SEG output)
FLD14 (SEG output)
FLD15 (SEG output)
1
0
FLD24 (SEG output)
FLD25 (SEG output)
FLD26 (SEG output)
FLD27 (SEG output)
FLD28 (SEG output)
FLD29 (SEG output)
FLD30 (SEG output)
FLD31 (SEG output)
Port P4
1
0
FLD40 (SEG output)
FLD41 (SEG output)
FLD42 (SEG output)
FLD43 (SEG output)
FLD44 (port output)
FLD45 (port output)
FLD46 (port output)
FLD47 (port output)
Port P5
0
FLD48 (port output)
FLD49 (port output)
FLD50 (port output)
FLD51 (port output)
FLD52 (port output)
FLD53 (port output)
FLD54 (port output)
FLD55 (port output)
Port P6
DIG output: This output is connected to digit of the FLD.
SEG output: This output is connected to segment of the FLD.
Port output: This output is general-purpose port (used by program).
The contents of digit output set switch registers
(0EF216, 0EF316)
FLD/Port switch registers
(0EF916 to 0EFB16)
Number of segments
Number of digits
The contents of digit output set switch registers
(0EF216, 0EF316)
FLD/Port switch registers
(0EF916 to 0EFB16)
DIG output: This output is connected to digit of the FLD.
SEG output: This output is connected to segment of the FLD.
Port output: This output is general-purpose port (used by program).
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