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参数资料
| 型号： | M38B79FFFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 48/112页 |
| 文件大小： | 1862K |
| 代理商： | M38B79FFFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
37
Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 opera-
tion.
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control
Fig. 37 Operation of clock synchronous serial I/O2 function
Fig. 36 Block diagram of clock synchronous serial I/O2
register (address 001D16) to “1”. For clock synchronous serial I/O,
the transmitter and the receiver must use the same clock for serial
I/O2 operation. If an internal clock is used, transmit/receive is
started by a write signal to the serial I/O2 transmit/receive buffer
register (TB/RB) (address 001F16).
When P67 (SCLK22) is selected as a clock I/O pin, SRDY2 output
function is invalid, and P66 (SCLK21) is used as an I/O port.
1/4
F/F
P66/SCLK21
P64/RXD
P65/TXD
P67/SRDY2/SCLK22
“0”
“1”
“0”
“1”
XIN
1/2
XCIN
“1”
“0”
P67/SRDY2/SCLK22
Serial I/O2 status register
Serial I/O2 control register
Receive buffer register
Address 001F16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O2 synchronous clock selection bit
Baud rate generator
Division ratio 1/(n+1)
Address 003716
BRG count source selection bit
Clock control circuit
Falling edge detector
Transmit buffer register
Data bus
Address 001F16
Shift clock
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001E16
Data bus
Address 001D16
Transmit shift register
Serial I/O2 clock I/O pin selection bit
Internal system clock selection bit
BRG clock
switch bit
Serial I/O2
clock I/O pin
selection bit
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transmit/Receive shift clock
(1/2 to 1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
Serial I/O2 input RxD
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F16)
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Receive enable signal SRDY2
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