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参数资料
| 型号： | M38B79FFFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 85/112页 |
| 文件大小： | 1862K |
| 代理商： | M38B79FFFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
71
CLOCK GENERATING CIRCUIT
The 38B7 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT or XCIN and XCOUT. Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. Af-
ter reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of XIN.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
s Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately af-
ter power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3 f(XCIN).
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
the main clock stop bit (bit 5) of the CPU mode register to “1”.
When the main clock XIN is restarted (by setting the main clock
stop bit to “0”), set enough time for oscillation to stabilize.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal system clock stops
at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2.
The bits of the timer 12 mode register are cleared to “0”. Set the
interrupt enable bits of the timer 1 and timer 2 to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts when an
external interrupt is received, but the internal system clock is not
supplied to the CPU until timer 2 underflows. This allows time for
the clock circuit oscillation to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops
at an “H” level. The states of XIN and XCIN are the same as the
state before executing the WIT instruction. The internal system
clock restarts at reset or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted.
Fig. 79 Ceramic resonator circuit
Fig. 80 External clock input circuit
XCIN
XCOUT
XIN
XOUT
CIN
COUT
CCIN
CCOUT
Rf
Rd
XIN
XOUT
External oscillation circuit
VCC
VSS
open
XCIN
XCOUT
External oscillation circuit
or external pulse
open
VCC
VSS
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