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参数资料
| 型号： | M58BW016DB90ZA6FT |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 512K X 32 FLASH 3V PROM, 90 ns, PBGA80 |
| 封装： | 10 X 12 MM, 1 MM PITCH, LBGA-80 |
| 文件页数： | 6/63页 |
| 文件大小： | 901K |
| 代理商： | M58BW016DB90ZA6FT |
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ing Synchronous Burst Read operations. Bus sig-
nals are latched on the active edge of the Clock.
The Clock can be configured to have an active ris-
ing or falling edge. In Synchronous Burst Read
mode the address is latched on the first active
clock edge when Latch Enable is low, VIL, or on
the rising edge of Latch Enable, whichever occurs
first.
During Asynchronous bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during Synchro-
nous Burst Read operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X-latency
time has expired. If Burst Address Advance is
Low, VIL, the internal address counter advances. If
Burst Address Advance is High, VIH, the internal
address counter does not change; the same data
remains on the Data Inputs/Outputs and Burst Ad-
dress Advance is not sampled until the Y-latency
expires.
The Burst Address Advance, B, may be tied to VIL.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be
used, during Synchronous Burst Read operations,
to identify if the memory is ready to output data or
not. The Valid Data Ready output can be config-
ured to be active on the clock edge of the invalid
data read cycle or one cycle before. Valid Data
Ready, at VIH, indicates that new data is or will be
available. When Valid Data Ready is Low, VIL, the
previous data outputs remain active.
In all Asynchronous operations, Valid Data Ready
is high-impedance. It may be tied to other compo-
nents with the same Valid Data Ready signal to
create a unique system Ready signal. The Valid
Data Ready output has an internal pull-up resistor
of around 1 M
powered from VDDQ, designers
should use an external pull-up resistor of the cor-
rect value to meet the external timing require-
ments for Valid Data Ready going to VIH.
Write Protect (WP). The Write Protect, WP, pro-
vides protection against program or erase opera-
tions. When Write Protect, WP, is at VIL the first
two (in the bottom configuration) or last two (in the
top configuration) parameter blocks and all main
blocks are locked. When Write Protect WP is at
VIH all the blocks can be programmed or erased, if
no other protection is used.
Supply Voltage (VDD). The Supply Voltage, VDD,
is the core power supply. All internal circuits draw
their current from the VDD pin, including the Pro-
gram/Erase Controller.
Output Supply Voltage (VDDQ). The Output Sup-
ply Voltage, VDDQ, is the output buffer power supply
for all operations (Read, Program and Erase) used
for DQ0-DQ31 when used as outputs.
Input Supply Voltage (VDDQIN). The Input Sup-
ply Voltage, VDDIN, is the power supply for all input
signal. Input signals are: K, B, L, W, GD, G, E, A0-
A18 and D0-D31, when used as inputs.
Program/Erase Supply Voltage (VPP). The Pro-
gram/Erase Supply Voltage, VPP, is used for pro-
gram and erase operations. The memory normally
executes program and erase operations at VPP1
voltage levels. In a manufacturing environment,
programming may be speeded up by applying a
higher voltage level, VPPH, to the VPP pin.
The voltage level VPPH may be applied for a total
of 80 hours over a maximum of 1000 cycles.
Stressing the device beyond these limits could
damage the device.
Ground (VSS and VSSQ). The Ground VSS is the
reference for the internal supply voltage VDD. The
Ground VSSQ is the reference for the output and
input supplies VDDQ, and VDDQIN. It is essential to
connect VSS and VSSQ together.
Note: A 0.1
F capacitor should be connected
between the Supply Voltages, VDD, VDDQ and
VDDIN and the Grounds, VSS and VSSQ to decou-
ple the current surges from the power supply.
The PCB track widths must be sufficient to car-
ry the currents required during all operations
of the parts, see Table 15, DC Characteristics,
for maximum current supply requirements.
Don’t Use (DU). This pin should not be used as it
is internally connected. Its voltage level can be be-
tween VSS and VDDQ or leave it unconnected.
Not Connected (NC). This pin is not physically
connected to the device.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M58BW016DB90ZA6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
| M58BW016DBT | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
| M58BW016DBZA | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
| M58BW016DT | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:16 Mbit (512 Kbit x 32, boot block, burst) 3 V supply Flash memories |
| M58BW016DT100T3T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
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