参数资料
型号: MA28140
厂商: Dynex Semiconductor Ltd.
英文描述: Packet Telecommand Decoder
中文描述: 包遥控解码器
文件页数: 27/72页
文件大小: 857K
代理商: MA28140
MA28140
27/72
5. PTD INTERFACES
5.1 PHYSICAL CHANNEL INTERFACE
Each TC channel consists of 3 input lines:
TCC
i
: symbol clock input
TCS
i
: symbol stream input (NRZ-L)
TCA
i
: channel active indication input
The maximum symbol rate with guaranteed operation
(using the internal AU) on these channels is 50 kbps. For
higher frequency, an incomplete AU process may occur
resulting in wrong signature calculation and thus rejected
frames. Without AU the symbol rate could be 200 kbps (not
guaranteed). At higher frequency, incorrect processing may
occur due to insufficient time to perform memory accesses.
The interface is composed of 6 TC channels. Figure 10 below
gives the timing associated with one of these 6 channels. For
unused channels, the TCA
i
signal should be connected to V
SS
,
and the TCC
i
and TCS
i
signals to V
DD
.
The DECOD output is activated when the CLTU decoder
state machine is in the decode state (see section 4.1). This
output goes high following the detection of a start sequence,
and goes low following a codeblock rejection or CLTU error.
5.2 MAP INTERFACE
The MAP interface allows the PTD to provide the on-board
applications with the TC segments stored in the back-end
buffer in the RAM. It is possible to transfer full TC segments
(including segment header and packet segment) with various
lengths, from 1 octet to 249 octets. The first data output is the
TC segment header. It is possible for an application to use
either a serial or parallel interface to read this TC data. The
choice between serial or parallel interface is made with the
configuration input pin PAR as follows:
PAR = 1; the parallel MAP interface is used (section 5.4)
PAR = 0; the serial MAP interface is used
The serial MAP interface consists of 5 signals.
MAPDSR, data set ready output,
MAPDTR, data terminal ready input,
MAPCK, MAP clock output,
MAPDATA, segment data output,
MAPADT, aborted data transfer output.
Figure 10: TC Channel Input Timing
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