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参数资料
| 型号： | MA28140 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | Packet Telecommand Decoder |
| 中文描述： | 包遥控解码器 |
| 文件页数： | 45/72页 |
| 文件大小： | 857K |
| 代理商： | MA28140 |
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MA28140
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CPDU Interface
CPDUSTN
O
CPDU address strobe signal. This signal allows the CPDU interface to latch the CPDU output
address present on the local data bus LDAT<7..0>. It is affected by the LACK input. Active low.
CPDU enable signal. This signal provides the command pulse with the appropriate duration.
Active high.
CPDU clock division selection input.
CPDUDIV = 0: the CPDU base clock (corresponding to D) is the system clock CLK divided by
40960.
CPDUDIV = 1: the CPDU base clock (corresponding to D) is the system clock CLK divided by
8192.
CPDUEN
O
CPDUDIV
I
CLCW Interface
CLCWSA
I
Nominal CLCW status sample. This signal indicates that the CLCW status is sampled by the
telemetry interface. Active low. This signal can be asynchronous
Nominal CLCW status clockout signal. This signal is provided to the PTD when CLCWSA
signal is active. This signal can be asynchronous
Nominal CLCW status data line (serial mode). The data is provided either on the falling edge of
CLCWSA or on the falling edge of CLCWCA.
Redundant CLCW status sample. Active low. This signal can be asynchronous
Redundant CLCW status clockout signal. This signal can be asynchronous
Redundant CLCW status data line (serial mode). The data is provided on the falling edge of
CLCWSB or on the falling edge of CLCWCB.
CLCWCA
I
CLCWDA
O
CLCWSB
CLCWCB
CLCWDB
I
I
O
Telemetry Interface
CPDUS/PCSN
I
CPDU status report sample. This signal indicates that the CPDU status report is sampled by the
telemetry interface in serial mode. Active low . This signal has the function parallel bus chip select
(PCSN) in parallel mode. This signal can be asynchronous
FAR status report first sample. This signal indicates that the first 16 bits of FAR are sampled in
serial mode. Active low. This signal has the function bit 2 of parallel address bus (PAD2) in
parallel mode. This signal can be asynchronous
FAR status report second sample. This signal indicates that the last 16 bits of FAR are sampled in
serial mode. Active low. This signal has the function bit 1 of parallel address bus (PAD1) in
parallel mode. This signal can be asynchronous
AUS status report first sample. This signal indicates that the first 16 bits of AUS are sampled in
serial mode. Active low. This signal has the function bit 0 of parallel address bus (PAD0) in
parallel mode. This signal can be asynchronous.
AUS status report second sample. This signal is used to read out the last 4 bits of the AU staus
report by asserting it four times. Active low. This signal can be asynchronous.
Common status clockout line used for CPDU, FAR and AUS (serial mode). This signal can be
asynchronous.
Common status data line for CPDU, FAR and AUS (serial mode). The data is provided on the
falling edge of CPDUS, FAR1S, FAR2S, AU1S or AU2S, or after the falling edge of TMC.
FAR1S/PAD2
I
FAR2S/PAD1
I
AU1S/PAD0
I
AU2S
I
TMC
I
TMD
O
Parallel Interface
PRDY
O
Parallel interface control line. This output is asserted when the data selected by PAD<2...0> is
available in parallel mode. Active low.
Parallel interface data bus PBUS<15..0> (PBUS0 being the LSB). PBUS tristate is controlled by
the PCSN input. When PCSN is deasserted PBUS is tristated.
PBUS<15..0>
O
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