- 您现在的位置：买卖IC网 > PDF目录383307 > MA28140 (Dynex Semiconductor Ltd.) Packet Telecommand Decoder PDF资料下载
参数资料
| 型号： | MA28140 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | Packet Telecommand Decoder |
| 中文描述： | 包遥控解码器 |
| 文件页数： | 7/72页 |
| 文件大小： | 857K |
| 代理商： | MA28140 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
MA28140
7/72
Priority Mode
In this mode two inputs have priority, according to the
following rule: TC0 > TC1 > TC2 = TC3 = TC4 = TC5. When
neither the TC0 input nor the TC1 input is active, the selection
between the inputs TC2 to TC5 is performed as in the
Standard Mode.
As soon as the TC active signal of TC0 is asserted, this TC
input is selected, and the 5 other channels are inhibited. In
case another input was already selected and receiving data, it
is abandoned. The TC0 input remains selected until one of the
following events:
a1: its TC active signal becomes inactive, or
b1: its bit clock has not been received for a period equal to
the TC clock timeout, or
c1: no Start Sequence has been detected for a period
equal to the TC active timeout, or
d1: a Tail Sequence or a codeblock rejection has occurred.
Upon events (a1) and (d1), the selection logic returns to
the search state. Upon events (b1) and (c1), the TC0 input is
ignored (i.e. considered inactive) until the event (a1) occurs.
When the TC0 input is inactive (including the case of a
timeout as described above), as soon as the TC active signal
of TC1 is asserted, this TC input is selected, and the lower
priority inputs TC2 to TC5 are inhibited. In case any of these
inputs was already selected and receiving data, it is
abandoned. The TCl input remains selected until one of the
following events.
a2: its TC active signal, becomes inactive, or
b2: its bit clock has not been received for a period equal to
the TC clack timeout, or
c2: no Start Sequence has been detected for a period
equal to the TC active timeout, or
d2: a Tail Sequence or a codeblock rejection has occurred,
or
e2: the TCO active signal is asserted.
Upon events (a2) and (d2), the selection logic returns to the
search state. Upon events (b2) and (c2), the selection logic
ignores the TC1 input until event (a2) occurs. Upon event (e2)
the TCl input is inhibited and the TC0 input is selected as
previously described.
The TC clock timeout value between two successive edges
of the TC channel clock is: 3932160 t
CK
< TC clock timeout <
4587520 t
CK
. With a system clock frequency f
CK
of 4 MHz this
equals 0.98s <TC clock timeout < 1.15s.
The TC active timeout value between two successive Start
Sequence patterns being detected is 334233600 t
CK
< TC
active timeout < 335399960 t
CK
. With a system clock
frequency f
CK
of 4MHz this equals 83.5s < TC active timeout <
83.9s.
Codeblock Decoding
Codeblock decoding is performed for each received
codeblock. At the sending end, a systematic block coding
procedure processing 56 bits per Codeblock and generating 7
parity check bits per Codeblock is used. The parity check bits
are then complemented and placed into the codeblocks: P0
(MSB) through P6 are located in the first seven bits (MSBs) of
the last octet of the codeblock. The last bit of the last octet, P7
(LSB), is a filler bit appended to complete the 8-bit Error Control
Field. This Filler Bit should normally be a zero, except for the
Tail Sequence. The code is a (63,56) modified Bose-Chaudhuri-
Hocquenghem (BCH), based on the following polynomial
generator: g(x)=x
7
+x
6
+x
2
+1. A single error correction & double
error detection mode is provided by using this code.
The following table describes the Decoding Strategy of the
codeblocks:
CLTU Management
CLTU decoding consists of the states and events
summarized in the following table and state diagram:
Figure 4: CLTU Decoder State Diagram
S1
INACTIVE
S2
SEARCH
S3
DECODE
E1
E3
E4
E2(c)
E2(a)
E2(b)
ERRORS DETECTED
FILLER BIT
VALUE
ignored
DECISION
no errors
codeblock
accepted
codeblock
rejected
codeblock
rejected
even number of errors
ignored
odd number of errors
with a binary syndrome
value equal to all zeros
odd number of errors
with a binary syndrome
value different from all
zeros
odd number of errors
with a binary syndrome
value different from all
zeros
ignored
0
codeblock
accepted
correction of
a single error
codeblock
rejected
1
相关PDF资料 |
PDF描述 |
|---|---|
| MA28151 | Radiation hard Programmable Communication Interface |
| MA28155 | Radiation Hard Programmable Peripheral Interface |
| MA31750 | High Performance MIL-STD-1750 Microprocessor |
| MA31751 | Memory Management & Block Protection Unit |
| MA31753 | DMA Controller (DMAC) For An MA31750 System |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MA28150FBB | 功能描述:专用陶瓷电容器 HF CHIP RoHS:否 制造商:Panasonic Electronic Components 电容:470 pF 容差:10 % 电压额定值:250 VAC 工作温度范围:- 25 C to + 125 C 端接类型:SMD/SMT 外壳代码 - in: 外壳代码 - mm: |
| MA28150FBN | 功能描述:专用陶瓷电容器 HF CHIP RoHS:否 制造商:Panasonic Electronic Components 电容:470 pF 容差:10 % 电压额定值:250 VAC 工作温度范围:- 25 C to + 125 C 端接类型:SMD/SMT 外壳代码 - in: 外壳代码 - mm: |
| MA28150GBB | 功能描述:专用陶瓷电容器 HF CHIP RoHS:否 制造商:Panasonic Electronic Components 电容:470 pF 容差:10 % 电压额定值:250 VAC 工作温度范围:- 25 C to + 125 C 端接类型:SMD/SMT 外壳代码 - in: 外壳代码 - mm: |
| MA28150GBN | 功能描述:专用陶瓷电容器 HF CHIP RoHS:否 制造商:Panasonic Electronic Components 电容:470 pF 容差:10 % 电压额定值:250 VAC 工作温度范围:- 25 C to + 125 C 端接类型:SMD/SMT 外壳代码 - in: 外壳代码 - mm: |
| MA28150JAB | 功能描述:专用陶瓷电容器 HF CHIP RoHS:否 制造商:Panasonic Electronic Components 电容:470 pF 容差:10 % 电压额定值:250 VAC 工作温度范围:- 25 C to + 125 C 端接类型:SMD/SMT 外壳代码 - in: 外壳代码 - mm: |
发布紧急采购，3分钟左右您将得到回复。