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参数资料
| 型号： | MA28140 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | Packet Telecommand Decoder |
| 中文描述： | 包遥控解码器 |
| 文件页数： | 44/72页 |
| 文件大小： | 857K |
| 代理商： | MA28140 |
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MA28140
44/72
7. SIGNAL DESCRIPTION
In this pin description, first the name of the pin is given, then its type (input (I) or output (O)), and then a brief description.
Total input pins
Total output pins
Total I/O pins
Total number of Input, Output and I/O pins
: 47
: 51
: 8
: 106
Note: Bit numbering convention: for busses, the bit number 0 is considered as the Least Significant Bit (LSB). For strobe
signals, it is indicated in the text if they are active on low or high level.
Transponder Interface
TCC0-TCC5
I
Symbol Clock signals. These signals are only recognised while Channel Active
Indication input is asserted. These signals can be asynchronous.
Symbol Stream signals. The data should be valid at the falling edge of the TCCi signals.
These signals can be asynchronous w.r.t. system clock, but not w.r.t. symbol clock signals.
Channel Active Indication signals. These signals serve as enable signals for the
Symbol Stream signals. Active high. These signals can be asynchronous.
TCS0-TCS5
I
TCA0-TCA5
I
Local Bus Interface
LADR<10..0>
O
Local Address Bus . This bus is unidirectional and is tristated when the BGRN signal is asserted.
LADR<0> is the LSB.
Data Bus - This 8 bit data bus is driven as outputs during write cycles and as inputs during read
cycles. This bus is tristated when the BGRN signal is asserted. LDAT<0> is the LSB.
Read/Write signal. This signal indicates the direction of the data transfer on the Local Bus and is
tristated when the BGRN signal is asserted.
RWN = 1: read mode.
RWN = 0: write mode.
Memory acknowledge signal. This signal allows wait state cycles to be inserted for memory (RAM,
ROM or LAC) read and write access and for CPDUSTN and MAPSTN outputs. LACK=0 inserts
wait states. LACK can be permanently connected to 1 when no wait states are required. This
signal can be asynchronous. Active high.
Bus request signal. This signal is asserted by an external unit to request the Local Bus (external
Authentication Unit for instance). Active low. This signal can be asynchronous.
Bus grant signal. This signal is asserted to allow an external unit to use the Local Bus. Active low.
Ram chip select signal. This signal is asserted during RAM access and is tristated when the
BGRN signal is asserted. It is affected by the LACK input. Active low.
Configuration Rom chip select signal. This signal is asserted during Configuration Rom access
and is tristated when the BGRN signal is asserted. It is affected by the LACK input. Active low.
Non volatile memory select signal. This signal is asserted during recovery LAC counter access
and is tristated when BGRN signal is asserted. It is affected by the LACK input. Active high.
LDAT<7..0>
I/O
RWN
O
LACK
I
BRQN
I
BGRN
RAMCSN
O
O
ROMCSN
O
LACCS
O
Map Interface
MAPSTN
O
MAP address strobe signal. This signal allows the MAP Demultiplexer circuitry to latch the MAP
identifier present on the local data bus. It is affected by the LACK input. Active low.
MAP clockout signal. This signal is only activated when both MAPDSR and MAPDTR signals are
active.
MAP data set ready signal. This output indicates that a TC segment is available for transfer.
Active high.
MAP data terminal ready signal. This signal indicates that the receiving device is ready to clock in
the segment data in serial mode or a segment data sample in parallel mode. Active high. This
signal can be asynchronous.
MAP segment data serial line. The segment data is clocked out on the falling edge of the MAPCK
signal.
MAP abort data transfer signal. This output is asserted when the PTD has aborted the transfer
of a TC segment. Active high.
MAPCK
O
MAPDSR
O
MAPDTR
I
MAPDATA
O
MAPADT
O
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