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参数资料
| 型号： | MAX1541ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/49页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIVIDER PWM 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 620kHz |
| 占空比： | 100% |
| 电源电压： | 2 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
Pin Description (continued)
MAX1540A
24
25
PIN
MAX1541
31
32
NAME
LX1
DH1
FUNCTION
Inductor Connection for Controller 1. Connect to the switched side of the inductor.
LX1 serves as the lower supply rail for the DH1 high-side gate driver.
High-Side Gate-Driver Output for Controller 1. DH1 swings from LX1 to BST1.
Open-Drain Power-Good Output. PGOOD1 is low when the output voltage is more
than 10% (typ) above or below the normal regulation point, during soft-start, and in
26
33
PGOOD1
shutdown. After the soft-start circuit has terminated, PGOOD1 becomes high
impedance if the output is in regulation. For the MAX1541, PGOOD1 is
blanked—forced high-impedance state—when FBLANK is enabled and the controller
detects a transition on GATE.
Output Voltage-Sense Connection for Controller 1. Connect directly to the positive
terminal of the output capacitors as shown in the standard application circuits
27
34
OUT1
(Figures 1 and 12). OUT1 senses the output voltage to determine the on-time for the
high-side switching MOSFET. For the MAX1540A, OUT1 also serves as the feedback
i t l 10 Ω i t t d b t OUT1 d d
input when using the preset internal output voltages as shown in Figure 10. When
discharge mode is enabled by OVP/UVP, the output capacitor is discharged through
Feedback Input for Controller 1:
MAX1540A: Connect to V CC for a +1.2V fixed output or to analog ground (GND) for a
28
35
FB1
+1.8V fixed output. For an adjustable output (0.7V to 5.5V), connect FB1 to a resistive
divider from OUT1. The FB1 regulation level is +0.7V.
MAX1541: The FB1 regulation level is set by the voltage at REFIN1.
Negative Current-Sense Input for Controller 1. Connect to the negative terminal of the
29
36
CSN1
current-sense element. Figure 14 and Table 9 describe several current-sensing
options. The PWM controller does not begin a cycle unless the current sensed is less
than the valley current-limit threshold programmed at ILIM1.
Positive Current-Sense Input for Controller 1. Connect to the positive terminal of the
30
37
CSP1
current-sense element. Figure 14 and Table 9 describe several current-sensing
options. The PWM controller does not begin a cycle unless the current sensed is less
than the valley current-limit threshold programmed at ILIM1.
Fault-Blanking Control Input. This four-level logic input enables or disables fault
blanking, and sets the forced-PWM operation time (t FBLANK ). When fault blanking is
enabled, PGOOD1 and the OVP/UVP protection for controller 1 are blanked for the
selected time period after the MAX1541 detects a transition on GATE. Additionally,
controller 1 enters forced-PWM mode for the duration of t FBLANK anytime GATE
—
38
FBLANK
changes states. Connect FBLANK as follows:
V CC = 220μs t FBLANK , fault blanking enabled.
Open = 140μs t FBLANK , fault blanking enabled.
REF = 65μs t FBLANK , fault blanking enabled.
GND = 140μs t FBLANK , fault blanking disabled.
See the Electrical Characteristics table for the t FBLANK limits.
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