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| 型号： | MAX1541ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 41/49页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIVIDER PWM 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 620kHz |
| 占空比： | 100% |
| 电源电压： | 2 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V SAG , output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
put voltages, it can produce three or more output volt-
ages if required by using discrete logic or a DAC.
Figure 15 shows an application circuit providing four
voltage levels using discrete logic. Switching resistors
in and out of the resistor network changes the voltage
1 - ? ?
? ?
V IN(MIN) =
V OUT + V DROP1
? h × t OFF(MIN) ?
K
at REFIN1. An edge-detection circuit is added to gen-
erate a 1μs pulse on GATE to trigger the fault blanking
and forced-PWM operation. When using PWM mode
( SKIP = V CC or open) on the main controller, the edge-
detection circuit is only required if fault blanking is
where V DROP1 is the parasitic voltage drop in the
charge path (see the On-Time One-Shot (TON) section),
t OFF(MIN) is from the Electrical Characteristics , and K is
taken from Table 3. The absolute minimum input voltage
is calculated with h = 1.
If the calculated V IN(MIN) is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain an
acceptable V SAG . If operation near dropout is anticipat-
ed, calculate V SAG to be sure of adequate transient
response.
enabled. Otherwise, leave OD unconnected.
Active Bus Termination
(MAX1541 OUT1 Only)
Active-bus-termination power supplies generate a volt-
age rail that tracks a set reference. They are required to
source and sink current. DDR memory architecture
requires active bus termination. In DDR memory archi-
tecture, the termination voltage is set at exactly half the
memory supply voltage. Configure the main MAX1541
controller (OUT1) to generate the termination voltage
using a resistive voltage-divider at REFIN1. In such an
?
V OUT2 = 2.5V
Dropout Design Example
application, the main MAX1541 controller (OUT1) must
be kept in PWM mode ( SKIP = V CC or open) in order
for it to source and sink current. Figure 16 shows the
?
?
?
?
?
f SW = 355kHz
K = 3.0μs, worst-case K MIN = 3.3μs
t OFF(MIN) = 500ns
V DROP1 = 100mV
h = 1.5
main MAX1541 controller configured as a DDR termina-
tion regulator. Connect GATE and FBLANK to GND
when unused.
1 - ? ?
V IN(MIN) =
2 . 5 V + 0 . 1 V
? 1.5 × 500ns ?
? 3 . 0 μ s ?
= 3 . 47 V
B
R4
R1
REF
REFIN1
? 3 . 3 μ s ?
Calculating again with h = 1 and the typical K-factor
value (K = 3.3μs) gives the absolute limit of dropout:
2 . 5 V + 0 . 1 V
V IN(MIN) =
= 3 . 06 V
? 1 × 500ns ?
1 - ? ?
Therefore, V IN must be greater than 3.06V, even with
very large output capacitance, and a practical input volt-
A
1.5k Ω
R3
1000pF
C1
R2
MAX1541
GND
GATE
age with reasonable output capacitance would be 3.47V.
Multi-Output Voltage Settings
(MAX1541 OUT1 Only)
1.5k Ω
1000pF
While the main MAX1541 controller (OUT1) is optimized
to work with applications that require two dynamic out-
Figure 15. Multi-Output Voltage Settings
______________________________________________________________________________________
41
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