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| 型号： | MAX1541ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 42/49页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIVIDER PWM 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 620kHz |
| 占空比： | 100% |
| 电源电压： | 2 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
V DDQ
V CC
V IN
SKIP
DH1
C IN
V TT = DDQ
10nF
10k Ω
10k Ω
LX1
REFIN1
DL1
MAX1541 GND
L
R SENSE
C OUT
V
2
CSP1
OD
CSN1
Figure 16. Active Bus Termination
GATE
FBLANK
OUT1
FB1
V DDQ = DDR MEMORY SUPPLY VOLTAGE
V TT = TERMINATION SUPPLY VOLTAGE
Voltage Positioning
In applications where fast load transients occur, the out-
put voltage changes instantly by ESR COUT x Δ I LOAD .
Voltage positioning allows the use of fewer output
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
capacitors for such applications, and maximizes the out-
put voltage AC and DC tolerance window in tight-toler-
ance applications.
Figure 17 shows the connection of OUT_ and FB_ in
voltage-positioned and nonvoltage-positioned circuits.
In nonvoltage-positioned circuits, the MAX1540A/
MAX1541 regulate at the output capacitor. In voltage-
positioned circuits, the MAX1540A/MAX1541 regulate
on the inductor side of the current-sense resistor.
V OUT_ is reduced to:
V OUT(VPS) = V OUT(NO LOAD) - R SENSE x I LOAD
?
?
?
Minimize current-sensing errors by connecting
CSP_ and CSN_ directly across the current-sense
resistor (R SENSE_ ).
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Route high-speed switching nodes (BST_, LX_,
Figure 18 shows the voltage-positioning transient
response.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 19). If possible, mount all the power compo-
nents on the top side of the board, with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
? Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
DH_, and DL_) away from sensitive analog areas
(REF, FB_, CSP_, CSN_).
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (N L _ source, C IN , C OUT _, and D L _
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N L _
and N H _ in order to keep LX_, GND, DH_, and the
DL_ gate-drive lines short and wide. The DL_ and
DH_ gate traces must be short and wide (50 mils to
100 mils wide if the MOSFET is 1in from the con-
?
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
troller IC) to keep the driver impedance low and for
proper adaptive dead-time sensing.
42
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