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| 型号： | MAX1541ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 33/49页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIVIDER PWM 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 620kHz |
| 占空比： | 100% |
| 电源电压： | 2 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
voltage during dynamic transitions. With the additional
capacitance, the REFIN1 voltage slews between the
MAX1540A/MAX1541
LX_
DL_
N L
L
R SENSE
C OUT
two set points with a time constant given by R EQ x
C REFIN1 , where R EQ is the equivalent parallel resis-
tance seen by the slew capacitor. Looking at Figure 12,
the time constant for a positive REFIN1 voltage transi-
τ POS = ?
? C REFIN1
GND
tion is:
? R8 × (R9+R10) ?
? R8+(R9+R10) ?
CSP_
and the time constant for a negative REFIN1 voltage
transition is:
CSN_
τ NEG = ?
? R8 × R9 ?
? R8+R9 ? REFIN1
OUT_
R C
? C
FB_
Linear Regulator (LDO)
R D
Figure 11. Setting V OUT with a Resistive Voltage-Divider at FB_
light loads, quickly discharging the output capacitors. If
fault blanking is enabled, the MAX1541 also disables
the main controller’s (OUT1) overvoltage and undervolt-
age fault protection, and forces PGOOD1 to a high-
impedance state for the period selected by FBLANK
(Table 6).
For a step-voltage change at REFIN1, the rate of
change of the output voltage is limited by the inductor
current ramp, the total output capacitance, the current
limit, and the load during the transition. The inductor
current ramp is limited by the voltage across the induc-
tor and the inductance. The total output capacitance
determines how much current is needed to change the
output voltage. Additional load current slows down the
output-voltage change during a positive REFIN1 volt-
age change, and speeds up the output-voltage change
during a negative REFIN1 voltage change. For fast pos-
itive output-voltage transitions, the current limit must be
greater than the load current plus the transition current:
The maximum input voltage for the linear regulator is
28V, while the minimum input voltage is determined by
the 800mV (max) dropout voltage (V LDOIN(MIN) =
V LDOOUT + V DROPOUT ) at 50mA load. Bypass the lin-
ear regulator ’s output (LDOOUT) with a 4.7μF or
greater capacitor, providing at least 1μF per 5mA of
internal and external load on the linear regulator. The
LDO can source up to 100mA for powering the con-
troller or supplying a small external load.
For the MAX1540A, the linear regulator provides the 5V
bias supply that powers the gate drivers and analog
controller (Figure 1), providing stand-alone capability.
The linear regulator’s input is internally connected to
the battery voltage input (LDOIN = V+), and the gate-
driver input supply is internally connected to the linear
regulator’s output (V DD = LDOOUT). Figure 13 is the
internal linear-regulator functional diagram.
For the MAX1541, the linear regulator supports Dual
Mode operation to allow the selection of a 5V output
voltage without requiring external components (Figure
1). Connect FBLDO to GND for a fixed 5.0V output. The
linear regulator’s output voltage can be adjusted from
1.25V to 5.5V using a resistive voltage-divider (Figure
12). The MAX1541 regulates FBLDO to a 1.25V feed-
back voltage. The adjusted output voltage is:
I LIMIT > I L OAD + C OUT V
V LDOOUT = V FBLDO ? 1 +
?
d
d t
?
?
R 11 ?
R 12 ?
Adding a capacitor across REFIN1 and GND filters
noise and controls the rate of change of the REFIN1
where V FBLDO = 1.25V. If unused, disable the MAX1541
linear regulator by connecting LDOON to GND.
______________________________________________________________________________________
33
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