参数资料
型号: MAX17080GTL+
厂商: Maxim Integrated Products
文件页数: 28/48页
文件大小: 0K
描述: IC CONTROLLER AMD SVI 40-TQFN
标准包装: 60
应用: 控制器,AMD SVI
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 0.013 V ~ 1.55 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
AMD 2-/3-Output Mobile Serial
VID Controller
t TRAN = ? NEW OLD ?
t TRAN ? OUT TARGET
controller reaches the target output voltage. At the end
of a downward VID transition, the upper PWRGD thresh-
old is enabled only after the output reaches the lower
VID code setting. Figure 5 shows VID transition timing.
The MAX17080 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an inter-
nal capacitor and current source programmed by
R TIME to transition the output voltage. The total transi-
tion time depends on R TIME , the voltage difference, and
the accuracy of the slew-rate controller (C SLEW
accuracy). The slew rate is not dependent on the total
output capacitance, as long as the surge current is less
than the current limit set by ILIM12 for the core SMPSs
and ILIM3 for the NB SMPS. For all dynamic positive
VID transitions or negative VID transitions in forced-
PWM mode (PSI_L set to 1), the transition time (t TRAN )
is given by:
? V ? V ?
( dV TARGET / dt )
where dV TARGET /dt = 6.25mV/μs × 143k ? /R TIME is the
slew rate, V OLD is the original output voltage, and V NEW
is the new target voltage. See the Slew-Rate Accuracy
in the Electrical Characteristics table for slew-rate limits.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an output
voltage transition is:
I L ? C OUT × ( dV TARGET / dt )
where dV TARGET /dt is the required slew rate and C OUT
is the total output capacitance of each phase.
If the SMPS is in a pulse-skipping mode (PSI_L set to
0), the discharge rate of the output voltage during
downward transitions is then dependent on the load
current and total output capacitance for loads less than
a minimum current, and dependent on the R TIME pro-
grammed slew rate for heavier loads. The critical load
current (I LOAD(CRIT) ) where the transition time is depen-
dent on the load is:
I LOAD ( CRIT ) ? C OUT × ( dV TARGET / dt )
For load currents less than I LOAD(CRIT) , the transition
time is:
C × dV
I LOAD
For soft-start, the controller uses a fixed slew rate of
1mV/μs. In shutdown, the outputs are discharged using
a 20 ? switch through the CSN_ pins for the core
SMPSs and through the OUT3 pin for the NB SMPS.
Forced-PWM Operation
After exiting the boot mode and if the PSI_L bit is set to
1, the MAX17080 operates with the low-noise, forced-
PWM control scheme. Forced-PWM operation disables
the zero-crossing comparator, forcing the low-side
gate-drive waveforms to constantly be the complement
of the high-side gate-drive waveforms. This keeps the
switching frequency constant and allows the inductor
current to reverse under light loads, providing fast,
accurate negative output-voltage transitions by quickly
discharging the output capacitors.
Forced-PWM operation comes at a cost: the no-load +5V
bias supply current remains between 50mA to 70mA,
depending on the external MOSFETs and switching fre-
quency. To maintain high efficiency under light load
conditions, the processor could switch the controller to a
low-power pulse-skipping control scheme.
Pulse-Skipping Operation
During soft-start and in power-saving mode—when the
PSI_L bit is set to 0—the MAX17080 operates in pulse-
skipping mode. Pulse-skipping mode enables the driver’s
zero-crossing comparator, so the driver pulls its DL low
when “zero” inductor current is detected (V GND - V LX =
0). This keeps the inductor from discharging the output
capacitors and forces the controller to skip pulses under
light load conditions to avoid overcharging the output.
In pulse-skipping operation, the controller terminates
the on-time when the output voltage exceeds the feed-
back threshold and when the current-sense voltage
exceeds the idle-mode current-sense threshold (V IDLE
= 0.15 x V LIMIT for the core SMPS and I LX3MIN = 0.25 x
I LX3PK setting for the NB SMPS). Under heavy load
conditions, the continuous inductor current remains
above the idle-mode current-sense threshold, so the
on-time depends only on the feedback voltage thresh-
old. Under light load conditions, the controller remains
above the feedback voltage threshold, so the on-time
duration depends solely on the idle-mode current-
sense threshold, which is approximately 15% of the full-
load peak current-limit threshold set by ILIM12 for the
core SMPSs and 25% of the full-load peak current-limit
threshold set by ILIM3 for the NB SMPS.
During downward VID transitions, the controller tem-
porarily sets the OVP threshold of the SMPSs to 1.85V
(typ), preventing false OVP faults. Once the error ampli-
fier detects that the output voltage is in regulation, the
OVP threshold tracks the selected VID DAC code.
28
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