参数资料
型号: MAX17080GTL+
厂商: Maxim Integrated Products
文件页数: 36/48页
文件大小: 0K
描述: IC CONTROLLER AMD SVI 40-TQFN
标准包装: 60
应用: 控制器,AMD SVI
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 0.013 V ~ 1.55 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
AMD 2-/3-Output Mobile Serial
VID Controller
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MAX17080
BST
DH
(R BST )*
C BST
N H
INPUT (V IN )
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5 ? in series with BST
slows down the high-side MOSFET turn-on time, elimi-
LX
V DD
C BYP
L
nating the shoot-through currents without degrading the
turn-off time (R BST in Figure 10). Slowing down the
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Offset and Address Change
for Core SMPSs (OPTION)
DL
PGND
(C NL )*
N L
The +12.5mV offset and the address change features
of the MAX17080 can be selectively enabled and dis-
abled by the OPTION pin setting. When the offset is
enabled, setting the PSI_L bit to 0 disables the offset,
reducing power consumption in the low-power state.
See the Core SMPS Offset section for a detailed
description of this feature.
(R BST )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
THE SWITCHING NODE RISE TIME.
(C NL )* OPTIONAL—THE CAPACITOR REDUCES LX-TO-DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 10. Gate-Drive Circuit
The internal pulldown transistor that drives DL low is
robust, with a 0.25 ? (typ) on-resistance. This helps pre-
In addition, the address of the core SMPSs can be
exchanged, allowing for flexible layout of the
MAX17080 with respect to the CPU placement on the
same or opposite sides of the PCB. Table 6 shows the
OPTION pin voltage levels and the features that are
enabled.
Table 6. OPTION Pin Settings
vent DL from being pulled up due to capacitive coupling
from the drain to the gate of the low-side MOSFETs
when the inductor node (LX) quickly switches from
ground to V IN . Applications with high input voltages and
long inductive driver traces could require rising LX
edges that do not pull up the low-side MOSFET’s gate,
causing shoot-through currents. The capacitive coupling
OPTION
V CC
3.3V
2V
GND
OFFSET
ENABLES
0
0
1
1
SMPS1
ADDRESS
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
SMPS2
ADDRESS
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
V GS ( TH ) > V IN ? RSS ?
between LX and DL created by the MOSFET’s gate-to-
drain capacitance (C RSS ), gate-to-source capacitance
(C ISS - C RSS ), and additional board parasitics should not
exceed the following minimum threshold:
? C ?
? C ISS ?
Typically, adding a 4700pF capacitor between DL and
power ground (C NL in Figure 10), close to the low-side
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
Note: VDD0 refers to CORE0 and VDD1 refers to CORE1 for
the AMD CPU.
Offset and Current-Limit Setting
for NB SMPS (ILIM3)
The offset and current-limit settings of the NB SMPS
can be set by the ILIM3 pin setting. Table 7 shows the
ILIM3 pin voltage levels and the corresponding settings
for the offset and current limit of the NB SMPS. The NB
offset is always present regardless of PSI_L setting.
The I LX3MIN minimum current-limit threshold in skip
mode is precisely 25% of the corresponding positive
current-limit threshold.
36
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