参数资料
型号: MAX17080GTL+
厂商: Maxim Integrated Products
文件页数: 39/48页
文件大小: 0K
描述: IC CONTROLLER AMD SVI 40-TQFN
标准包装: 60
应用: 控制器,AMD SVI
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 0.013 V ~ 1.55 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
AMD 2-/3-Output Mobile Serial
VID Controller
Core Input Capacitor Selection
The input capacitor must meet the ripple-current
requirement (I RMS ) imposed by the switching currents.
For a dual 180 ° interleaved controller, the out-of-phase
operation reduces the RMS input ripple current, effec-
tively lowering the input capacitance requirements.
FBAC pin. Based on the configuration shown in Figure
4, the ripple voltage at the FBDC pin can only be less
than, or equal to, the ripple at the FBAC pin.
With the requirement that R FBDC = R FBAC , and
(Z CFB //R FB ) < 10% of R FBAC , then:
C OUT SW SENSE Gm ( FBAC )
When both outputs operate with a duty cycle less than
50% (V IN > 2V OUT ), the RMS input ripple current is
defined by the following equation:
R FBAC = R FBDC ≥
f R
1
? ? I OUT 1 ( I OUT 1 ? I IN ) + ? ? V
? ? I OUT 2 ( I OUT 2 ? I IN )
I RMS =
? V OUT1 ? ? V OUT 2 ?
?
? V IN I N
where Gm (FBAC_) is typically 2mS as defined in the
Electrical Characteristics table, R SENSE_ is the effective
value of the current-sense element that is used to pro-
I IN = ? OUT 1 ? I OUT 1 + ? OUT 2 ? I OUT 2
I RMS OUT ? OUT ? ? ? OUT ?
? V ? ? 1 V ?
R DROOP _ AC ≈ FBDC FBAC SENSE Gm ( FBA C )
where I IN is the average input current:
? V ? ? V ?
? V IN ? ? V IN ?
In combined mode (GNDS1 = V DDIO or GNDS2 =
V DDIO ) with both phases active, the input RMS current
simplifies to:
= I
? V IN ? ? 2 V IN ?
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due
to their resistance to inrush surge currents typical of
systems with a mechanical switch or connector in
series with the input. If the MAX17080 is operated as
the second stage of a two-stage power-conversion sys-
tem, tantalum input capacitors are acceptable. In either
configuration, choose an input capacitor that exhibits
less than +10 ° C temperature rise at the RMS input cur-
rent for optimal circuit longevity.
Core Voltage Positioning and Loop Compensation
vide the (CSP_, CSN_) current-sense voltage, and f SW
is the selected switching frequency.
Based on the above requirement for R FBAC and R FBDC ,
and with the other requirement for R FBDC defined in the
Core Steady-State Voltage Positioning (DC Droop) sec-
tion, R FBAC and R FBDC can be chosen. The resultant
AC droop is:
R R R
R FBAC + R FBDC
Capacitor C FB is required when the R DROOP_DC is less
than R DROOP_AC . Choose C FB according to the following
equation:
C FB × ?? R FB / /( R FBAC + R FBDC ) ?? = 3 × t SW
Core Steady-State Voltage Positioning
With R DROOP_AC defined, the steady-state voltage-
positioning slope, R DROOP_DC , can only be less than,
or at most equal to, R DROOP_AC :
R FBDC FBAC SENSE
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the output
capacitance and processor’s power-dissipation require-
R DROOP _ DC =
R R
R FBAC + R FBDC + R FB
Gm ( FBAC )
ments. The controller uses a transconductance amplifier
to set the transient AC and DC output-voltage droop
(Figure 4). The FBAC and FBDC configuration adjusts
the steady-state regulation voltage as a function of the
load. This adjustability allows flexibility in the selected
current-sense resistor value or inductor DCR, and allows
smaller current-sense resistance to be used, reducing
the overall power dissipated.
Core Transient Droop and Stability
The inductor current ripple sensed across the current-
sense inputs (CSP_ - CSN_) generates a proportionate
current out of the FBAC pin. This AC current flowing
across the effective impedance at FBAC generates an
AC ripple voltage. Actual stability, however, depends
on the AC voltage at the FBDC pin, and not on the
Choose the R FBDC and R FBAC already previously cho-
sen, then select R FB to give the desired droop.
DC droop is typically used together with the +12.5mV
offset feature to keep within the DC tolerance window of
the application. See the Offset and Address Change for
Core SMPSs (OPTION) section.
Core Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high-load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N H ) must be able to dissipate
the resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both of these sums.
______________________________________________________________________________________
39
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