参数资料
型号: MAX17080GTL+
厂商: Maxim Integrated Products
文件页数: 43/48页
文件大小: 0K
描述: IC CONTROLLER AMD SVI 40-TQFN
标准包装: 60
应用: 控制器,AMD SVI
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 0.013 V ~ 1.55 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
AMD 2-/3-Output Mobile Serial
VID Controller
DATA OUTPUT
BY MASTER
D7
D6
D0
NOT ACKNOWLEDGE
DATA OUTPUT
BY MAX17080
ACKNOWLEDGE
SVC FROM
MASTER
1
CLK1
2
CLK2
8
CLK8
9
CLK9
S
START
CONDITION
ACKNOWLEDGE
CLOCK PULSE
Figure 12. SVI Bus Acknowledge
START
STOP
S
SLAVE ADDRESS
SET DAC AND PSI_L
P
FIXED VALUES
Figure 13. SVI Bus Data Transfer Summary
Bus Not Busy
The SVI bus is not busy when both data and clock lines
remain high. Data transfers can be initiated only when
the bus is not busy. Figure 12 shows the SVI bus
acknowledge.
Start Data Transfer (S)
Starting from an idle bus state (both SVC and SVD are
high), a high-to-low transition of the data (SVD) line while
the clock (SVC) is high determines a START condition.
All commands must be preceded by a START condition.
Stop Data Transfer (P)
A low-to-high transition of the SDA line while the clock
(SVC) is high determines a STOP condition. All opera-
tions must be ended with a STOP condition.
Slave Address
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (110xxxx) for the MAX17080. Since the
MAX17080 is a write-only device, the eighth bit of the
slave address is 0. The MAX17080 monitors the bus for
its corresponding slave address continuously. It gener-
ates an acknowledge bit if the slave address was true
and it is not in a programming mode.
SVD Data Valid
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the high period of the clock signal. The data
on the line must be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
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43
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