参数资料
型号: MAX17080GTL+
厂商: Maxim Integrated Products
文件页数: 45/48页
文件大小: 0K
描述: IC CONTROLLER AMD SVI 40-TQFN
标准包装: 60
应用: 控制器,AMD SVI
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 0.013 V ~ 1.55 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
AMD 2-/3-Output Mobile Serial
VID Controller
noise generated by the power components. Follow
these guidelines for good PCB layout:
? Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
? Connect all analog grounds to a separate solid cop-
per plane; then connect the analog ground to the
GND pins of the controller. The following sensitive
components connect to analog ground: V CC and
V DDIO bypass capacitors, remote sense and GNDS
bypass capacitors, and the resistive connections
(ILIM12, OSC, TIME).
? Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBx (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single m ?
of excess trace resistance causes a measurable effi-
ciency penalty.
? Connections for current limiting (CSP, CSN) and volt-
age positioning (FBS, GNDS) must be made using
Kelvin-sense connections to guarantee the current-
sense accuracy. Place current-sense filter capacitors
and voltage-positioning filter capacitors as close as
possible to the IC.
? Route high-speed switching nodes and driver traces
away from sensitive analog areas (REF, V CC , FBAC,
FBDC, OUT3, etc.). Make all pin-strap control input
connections ( SHDN , PGD_IN, OPTION) to analog
ground or V CC rather than power ground or V DD .
? Route the high-speed serial-interface signals (SVC,
SVD) in parallel, keeping the trace lengths identical.
Keep the SVC and SVD away from the high-current
switching paths.
? Keep the drivers close to the MOSFET, with the gate-
drive traces (DL, DH, LX, and BST) short and wide to
minimize trace resistance and inductance. This is
essential for high-power MOSFETs that require low-
impedance gate drivers to avoid shoot-through cur-
rents.
? When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example, it
is better to allow some extra distance between the
input capacitors and the high-side MOSFET rather than
to allow distance between the inductor and the low-
side MOSFET or between the inductor and the output
filter capacitor.
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, C IN ,
C OUT , and DL anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas. For the NB SMPS, place CIN3 and L3
as near as possible to the MAX17080, using multi-
ple vias to reduce inductance when connecting the
different layers.
2) Use multiple vias to connect the exposed backside to
the power ground plane (PGND) to allow for a low-
impedance path for the SMPS3 internal low-side
MOSFET.
3) Mount the MAX17080 close to the low-side
MOSFETs. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the driver IC).
4) Group the gate-drive components (BST capacitors,
V DD bypass capacitor) together near the
MAX17080.
5) Make the DC-DC controller ground connections as
shown in the standard application circuit (Figure 2).
This diagram can be viewed as having three sepa-
rate ground planes: input/output ground, where all
the high-power components go; the power ground
plane, where the PGND, V DD bypass capacitor,
and driver IC ground connection go; and the con-
troller’s analog ground plane, where sensitive ana-
log components, the MAX17080’s AGND pin, and
V CC bypass capacitor go. The controller’s analog
ground plane (AGND) must meet the power ground
plane (PGND) only at a single point directly beneath
the IC. The power ground plane should connect to
the high-power output ground with a short, thick
metal trace from PGND to the source of the low-side
MOSFETs (the middle of the star ground).
6) Connect the output power planes (V CORE , V OUT3 ,
and system ground planes) directly to the output
filter capacitor positive and negative terminals with
multiple vias. Place the entire DC-DC converter
circuit as close to the CPU as is practical.
______________________________________________________________________________________
45
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