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| 型号： | MAX8550AETI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/29页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUP DDR INTEG 28TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 控制器，DDR |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 2 |
| 输出电压： | 1.8V，2.5V，0.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 管件 |
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Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Stability Requirements
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
VTT Output Capacitor Selection (LDO)
A minimum value of 60μF is needed to stabilize the VTT
output for load currents up to ±1.5A. This value of capaci-
tance limits the regulator’s unity-gain bandwidth frequen-
cy to about 700kHz (typ) to allow adequate phase margin
for stability. To keep the capacitor acting as a capacitor
f ESR ≤ SW
f ESR =
where :
f
π
1
2 π × R ESR × C OUT
within the regulator’s bandwidth, it is important that
ceramic caps with low ESR and ESL be used.
Since the gain bandwidth is also determined by the
transconductance of the output FETs, which increases
with load current, the output capacitor needs to be
greater than 60μF if the load current exceeds 1.5A, but
can be smaller than 60μF if the maximum load current
If C OUT consists of multiple same-value capacitors, as
in the Typical Applications Circuit of Figure 8, the f ESR
remains the same as that of a single capacitor.
For a typical 600kHz application, the ESR zero frequen-
is less than 1.5A. As a rule, choose the minimum
capacitance and maximum ESR for the output capaci-
tor using the following:
cy must be well below 190kHz, preferably below
100kHz. Two 150μF/4V Sanyo POS capacitors are used
to provide 12m Ω (max) of R ESR . This results in a zero at
42kHz, well within the bounds of stability.
Do not put high-value ceramic capacitors directly
C OUT _ MIN = 60 μ F ×
R ESR _ MAX = 5 m Ω ×
I LOAD
1 . 5 A
1 . 5 A
I LOAD
across the feedback sense point without taking precau-
tions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
R ESR value is measured at the unity-gain-bandwidth
frequency given by approximately:
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
f GBW =
40
C OUT
×
I LOAD
1 . 5 A
which should be as close as possible to the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and fast-feed-
back loop instability. Double pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum off-
time period has expired.
Double pulsing is more annoying than harmful, result-
ing in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped but can
cause the output voltage to rise above or fall below the
tolerance limits. The easiest method for checking stabil-
ity is to apply a very fast zero-to-max load transient and
carefully observe the output-voltage-ripple envelope for
overshoot and ringing. It can help to simultaneously
monitor the inductor current with an AC current probe.
Do not allow more than one cycle of ringing after the
initial step-response under/overshoot.
Once these conditions for stability are met, additional
capacitors, including those of electrolytic and tantalum
types, can be connected in parallel to the ceramic
capacitor (if desired) to further suppress noise or volt-
age ripple at the output.
VTTR Output Capacitor Selection (LDO)
The VTTR buffer is a scaled-down version of the VTT
regulator, with much smaller output transconductance.
Its compensation cap can therefore be smaller, and its
ESR larger, than what is required for its larger counter-
part. For typical applications requiring load current up
to ±15mA, a ceramic cap with a minimum value of 1μF
is recommended (R ESR < 0.3 Ω ). Connect this cap
between VTTR and the analog ground plane.
VTTI Input Capacitor Selection (LDO)
Both the VTT and VTTR output stages are powered
from the same VTTI input. Their output voltages are ref-
erenced to the same REFIN input. The value of the VTTI
bypass capacitor is chosen to limit the amount of rip-
ple/noise at VTTI, or the amount of voltage dip during a
load transient. Typically VTTI is connected to the output
of the buck regulator, which already has a large bulk
20
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8550AETI+ | 功能描述:电压模式 PWM 控制器 Integrated DDR Power Supply Solution RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| MAX8550AETI+T | 功能描述:电压模式 PWM 控制器 Integrated DDR Power Supply Solution RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| MAX8550AETI-T | 功能描述:PMIC 解决方案 RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8550ETI | 功能描述:PMIC 解决方案 RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8550ETI+ | 功能描述:电压模式 PWM 控制器 Integrated DDR Power Supply Solution RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
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