- 您现在的位置：买卖IC网 > PDF目录13110 > MAX8550AETI+ (Maxim Integrated Products)IC PWR SUP DDR INTEG 28TQFN PDF资料下载
参数资料
| 型号： | MAX8550AETI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/29页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUP DDR INTEG 28TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 控制器，DDR |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 2 |
| 输出电压： | 1.8V，2.5V，0.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
capacitor. Nevertheless, a ceramic capacitor of at least
10μF must be used and must be added and placed as
close as possible to the VTTI pin. This value must be
increased with larger load current, or if the trace from
the VTTI pin to the power source is long and has signifi-
cant impedance. Furthermore, to prevent undesirable
VTTI bounce from coupling back to the REFIN input
and possibly causing instability in the loop, the REFIN
pin should ideally tap its signal from a separate low-
impedance DC source rather than directly from the
VTTI input. If the latter is unavoidable, increase the
amount of bypass capacitance at the VTTI input and
add additional bypass at the REFIN pin.
MOSFET Selection (Buck)
Use R DS(ON) at T J(MAX) :
P LSDC = 2 I LOAD × V F × t DT × f SW
where V F is the body-diode forward-voltage drop, t DT is
the dead time ( ≈ 30ns), and f SW is the switching fre-
quency. Because of the zero-voltage switch operation,
the low-side MOSFET gate-drive loss occurs as a result
of charging and discharging the input capacitance,
(C ISS ). This loss is distributed among the average DL
gate-driver ’s pullup and pulldown resistance, R DL
( ≈ 1 Ω ), and the internal gate resistance (R GATE ) of the
MOSFET ( ≈ 2 Ω ). The drive power dissipated is given by:
The MAX8550A drives external, logic-level, n-channel
MOSFETs as the circuit-switch elements. The key
selection parameters:
P LSDR = C ISS × V GS 2 × f SW ×
R GATE
R GATE + R DL
On-resistance (R DS(ON) ): the lower, the better.
Maximum drain-to-source voltage (V DSS ): should be
at least 20% higher than input supply rail at the high-
side MOSFET’s drain.
Gate charges (Q G , Q GD , Q GS ): the lower the better.
Choose MOSFETs with rated R DS(ON) at V GS = 4.5V.
For a good compromise between efficiency and cost,
choose the high-side MOSFET that has a conduction
loss equal to its switching loss at nominal input voltage
and maximum output current (see below). For the low-
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses:
? The channel-conduction loss (P HSCC )
? The VI overlapping switching loss (P HSSW )
? The drive loss (P HSDR )
(The high-side MOSFET does not have body-diode
conduction loss because the diode never conducts
current):
× I LOAD DS ( ON )
× R
side MOSFET, make sure that it does not spuriously
turn on because of dV/dt caused by the high-side
MOSFET turning on, as this results in shoot-through
P HSCC =
V OUT
V IN
2
current degrading efficiency. MOSFETs with a lower
Q GD to Q GS ratio have higher immunity to dV/dt.
Use R DS(ON) at T J(MAX) :
For proper thermal-management design, calculate the
power dissipation at the desired maximum operating
junction temperature, maximum output current, and
P HSSW = V IN × I LOAD × f SW ×
Q GS + Q GD
I GATE
worst-case input voltage. For the low-side MOSFET, the
worst case is at V IN(MAX) . For the high-side MOSFET,
the worst case could be at either V IN(MIN) or V IN(MAX) .
where I GATE is the average DH-driver output current
determined by:
The high-side MOSFET and low-side MOSFET have dif-
ferent loss components due to the circuit operation.
The low-side MOSFET operates as a zero-voltage
I GATE ( ON ) =
2 . 5 V
R DH + R GATE
switch; therefore, major losses are:
? The channel-conduction loss (P LSCC )
? The body-diode conduction loss (P LSDC )
where R DH is the high-side MOSFET driver’s on-resis-
tance (1 Ω typ) and R GATE is the internal gate resis-
tance of the MOSFET ( ≈ 2 Ω ):
P LSCC = ? 1 -
× I LOAD DS ( ON )
× R
? The gate-drive loss (P LSDR ):
? V OUT ? 2
?
? V IN ?
P HSDR = Q G × V GS × f SW ×
R GATE
R GATE + R DH
______________________________________________________________________________________
21
相关PDF资料 |
PDF描述 |
|---|---|
| MAX8632ETI+ | IC PWR SUPPLY DDR 28-TQFN |
| VE-J1B-CZ-B1 | CONVERTER MOD DC/DC 95V 25W |
| ASC15DRAN | CONN EDGECARD 30POS .100 R/A DIP |
| MAX17582GTM+ | IC PWM CTRLR STP-DN DL 48TQFN |
| RMM18DTAS | CONN EDGECARD 36POS R/A .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8550AETI+ | 功能描述:电压模式 PWM 控制器 Integrated DDR Power Supply Solution RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| MAX8550AETI+T | 功能描述:电压模式 PWM 控制器 Integrated DDR Power Supply Solution RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| MAX8550AETI-T | 功能描述:PMIC 解决方案 RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8550ETI | 功能描述:PMIC 解决方案 RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8550ETI+ | 功能描述:电压模式 PWM 控制器 Integrated DDR Power Supply Solution RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。