MB89190/190A series
Chapter 12 A/D Converter
12-5
Clock selector
This selects the clock for starting the A/D conversion and the sense function, with continuous start
enabled (ADC2: EXT = 1).
Analog channel selector
This circuit selects one of the eight analog input pins.
Sample hold circuit
This circuit holds the input voltage selected by the analog channel selector.
By sampling and holding the input voltage immediately after A/D conversion or sense function is
started, the conversion can be made without being affected by changes in the input voltage during A/D
conversion (during A/D comparison).
D/A converter
This generates a voltage corresponding to the value set in the ADCD register.
Comparator
This compares the input voltage that was sampled and held and the output voltage of the D/A
converter to determine greater-than or smaller-than.
Control circuit
The control circuit has the following two functions:
– The A/D conversion function sequentially compares the bits of the ADCD register from the most
significant bit to the least significant bit according to the greater-than or smaller-than signal from the
comparator to determine the values. After conversion, the A/D conversion function sets the interrupt
request flag bit (ADC1: ADI).
– The sense function sets the interrupt request flag bit (ADI) when the greater-than or smaller-than
signal from the comparator matches the condition of the comparison-condition setting bit (SIFM) of
the ADC1 register.
A/D data register (ADCD)
The ADCD register has the following two functions:
– The A/D conversion function stores the result of the A/D conversion.
– The sense function writes the data on the voltage to be compared to the input voltage.
A/D control register 1 (ADC1)
This register enables and disables each function, selects analog input pins, checks the state, and
performs interrupt control.
A/D control register 2 (ADC2)
This register selects input clocks, enables and disables interrupts, select functions, etc.
Interrupt related to A/D converter
IRQ6: The interrupt request occurs when the interrupt request output is already enabled (ADC2:
ADIE = 1) when A/D conversion completion and the condition set at sense function.