MB89190/190A series
Chapter 8 8-bit Serial I/O
8-19
8.
9 Notes on Using 8-bit Serial I/O
Notes on using the 8-bit serial I/O are explained.
T Notes on using 8-bit serial I/O
Error at start of serial transfer
Starting using the serial transfer program (SMR: SST = 1) and the falling (output) or rising (input)
edges of the shift clock are asynchronous, so I/O of the first serial data is delayed by the shift clock
cycle set at maximum.
Malfunction due to noise
Serial I/O may malfunction if there is an extra pulse (exceeding the hysteresis width) caused by
external noise in the shift clock during serial data transfer.
Notes when setting using program
– Write to the serial mode register (SMR) or serial data register (SDR) when serial I/O is stopped
(SMR: SST = 0).
– When starting/enabling serial I/O transfer (SMR: SST = 1), do not change other bits of the SMR
register.
– When using the shift clock as the external shift clock input, the output level of the SO pin is the
most significant bit even when the serial I/O transfer is stopped (SMR: SST = 0) if serial data output
is enabled (SMR: SOE = 1) and if MSB first is set at the external shift clock input time. It is the
least significant bit even when serial I/O transfer is stopped (SMR: SST = 0) if serial data output is
enabled (SMR: SOE = 1) and if LSB first is set at the external shift clock input time.
– The interrupt request flag bit (SMR: SIOF) is not set when serial I/O transfer stop (SMR: SST = 0)
and serial data transfer completion occur at the same time.
– Control cannot return from interrupt processing when the SIOF bit is 1 and interrupt request output
is enabled (SIOE = 1). Always clear the SIOF bit.
Serial I/O baud rate
The serial data output pin (SO) of the serial I/O is an N-CH open-drain output, so it is unsuitable for
high-speed transfer. Take care when using a high-speed shift clock.
Idle state of shift clock
Set the external shift clock to H level during the wait time (idle state) between one 8-bit data transfer
and another one. When the internal shift clock (SMR: CKS1, 0 = other than 11B) is used as the shift
clock output (SMR: SCKE = 1), the output is H level in the idle state.
Figure 8.9 shows the idle state of the shift clock.
Fig. 8.9 Idle State of Shift Clock
External shift
clock
8-bit data transfer
Idle state
8-bit data transfer
Idle state