MB89190/190A series
Chapter 10 External Interrupt Circuit 1 (Edge)
10-9
Table 10-4-1 Function of Each Bit of External Interrupt 1 Control Register 1 (EIC1)
Bit name
Function
Bit 7
EIR1:
External interrupt
request flag bit 1
Set to 11B when edge selected by edge polarity selection bits 1 (SL11, SL10) input
to external interrupt pin INT11
Interrupt request output when this bit and interrupt request enable bit 1 (EIE1) are
1
Bit cleared when 0 written. Unaffected when 1 written
Bit 6
Bit 5
SL11SL10:
Edge polarity
selection bit 1
Select polarity of edge of pulse input to external interrupt pin INT11 that becomes
interrupt factor
When 00B, no edge detected and no interrupt request occurs
When 01B, rising edge detected
When 10B, falling edge detected
When 11B, both rising and falling edges detected
Bit 4
EIE1:
Interrupt request
enable bit 1
Enables/disables interrupt request output to CPU.
Interrupt request output when this bit and external interrupt request flag bit 1 (EIR1)
are 1
For reference:
When using external interrupt pin, write 0 to bit 5 of port direction register (DDR3)
to set pin to input.
State of external interrupt pin read directly from port data register (PDR3)
irrespective of state of interrupt request enable bit
Bit 3
EIR0:
External interrupt
request flag bit 0
Set to 11B when edge selected by edge polarity selection bits 1 (SL01, SL00)
input to external Interrupt pin INT10
Interrupt request output when this bit and interrupt request enable bit 0 (EIE0) are
1
Bit cleared when 0 written. Unaffected when 1
Bit 2
Bit 1
SL01SL00:
Edge polarity
selection bit 0
Select polarity of edge of pulse input to external interrupt pin INT10 that becomes
interrupt factor
When 00B, no edge detected and no interrupt request occurs
When 01B, rising edge detected.
When 10B, falling edge detected
When 11B, both rising and falling edges detected
Note: When an edge is selected when no edge detection is in effect, an edge may
be detected. So always clear the EIR0 bit after edge selection.
Bit 0
EIE0:
Interrupt request
enable bit 0
Enables/disables interrupt request output to CPU. Interrupt request output when
this bit and external interrupt request flag bit 0 (EIR0) are 1
Remarks:
When using external interrupt pin, write 0 to bit 4 of port direction register (DDR3)
to set pin to input
State of external interrupt pin read directly from port data register (PDR3)
irrespective of state of interrupt request enable bit