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参数资料
| 型号： | MC68HC05C5CP |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | DIP-40 |
| 文件页数： | 21/58页 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CP |
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Page 22
MOTOROLA
Section 4: CPU Core
MC68HC05C5 Specification Rev. 1.2
4.3.5
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective address of the argument is
contained in the 8-bit index register. This addressing mode can access the first 256
memory locations. These instructions are only 1 byte long. This mode is often used to
move a pointer through a table or to hold the address of a frequently referenced RAM or
I/O location.
4.3.6
INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the unsigned byte following the opcode.
This addressing mode is useful for selecting the K
th element in an n element table. With
this 2-byte instruction, K would typically be in X and the address of the beginning of the
table would be in the instruction. As such, tables may begin anywhere within the first 256
addressable locations and could extend as far as location 510 ($01FE). This is the last
location which can be accessed in this way.
4.3.7
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the 2 unsigned bytes following the
opcode. This address mode can be used in a manner similar to indexed, 8-bit offset
except that this 3-byte instruction allows tables to be anywhere in memory. As with direct
and extended addressing, the Motorola assembler determines the shortest form of
indexed addressing.
4.3.8
BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and
the byte following the opcode specifies the direct addressing of the byte in which the
specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory,
including I/O, can by selectively set or cleared with a single 2-byte instruction.
4.3.9
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and
relative addressing. The bit that is to be tested and its condition (set or clear), is included
in the opcode. The address of the byte to be tested is in the single byte immediately
following the opcode byte. The signed relative 8-bit offset in the third byte is added to the
PC if the specified bit is set or cleared in the specified memory location. This single 3-
byte instruction allows the program to branch based on the condition of any readable bit
in the first 256 locations of memory. The span of branching is from -128 to +127 from the
address of the next opcode. The state of the tested bit is also transferred to the carry bit
of the condition code register.
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