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参数资料
| 型号： | MC68HC05C5CP |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | DIP-40 |
| 文件页数： | 28/58页 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CP |
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Page 28
MOTOROLA
Section 4: CPU Core
MC68HC05C5 Specification Rev. 1.2
4.6
LOW-POWER MODES
4.6.1
STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP
mode, the internal oscillator is turned off, halting all internal processing, including timer
and COP Watchdog operation. The RC oscillator is also turned off during STOP mode,
and is not available for use by the EEPROM system.
During the STOP mode, the TCR bits are altered to remove any pending timer interrupt
request and to disable any further timer interrupts. The timer prescaler is cleared. The I
bit in the CCR is cleared to enable external interrupts. All other registers and memory
remain unaltered.
All input/output lines remain unchanged.
The processor can be
brought out of the STOP mode only by an external interrupt or reset.
4.6.1.1
STOP RECOVERY
The processor can be brought out of the STOP mode only by an external interrupt or
RESET. See Figure 4-5.
Figure 4-5: Stop Recovery Timing Diagram
1FFE
1FFF
INTERNAL
ADDRESS
BUS
INTERNAL
CLOCK
IRQ
3
IRQ
2
RESET
OSC1
1
t
ILCH
4064 t
cyc
RESET OR INTERRUPT
VECTOR FETCH
t
LIH
t
RL
Notes:
1.
Represents the internal gating of the OSC1 pin.
2.
IRQ pin edge-sensitive mask option.
3.
IRQ pin level- and edge-sensitive mask option.
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