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参数资料
| 型号： | MC68HC05C5CP |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | DIP-40 |
| 文件页数： | 22/58页 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CP |
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Page 23
Section 4: CPU Core
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
4.3.10
INHERENT
In the inherent addressing mode, all the information necessary to execute the instruction
is contained in the opcode.
Operations specifying only the index register and/or
accumulator as well as the control instructions with no other arguments are included in
this mode. These instructions are 1 byte long.
4.4
RESETS
The MCU can be reset three ways: by the initial power-on reset function, by an active low
input to the RESET pin, and by a COP watchdog-timer reset.
4.4.1
POWER-ON RESET (POR)
An internal reset is generated upon power-up to allow the internal clock generator to
stabilize. The power-on reset is strictly for power turn-on conditions and should not be
used to detect a drop in the power supply voltage. There is a 4064 internal processor
clock cycle (t
CYC
) oscillator stabilization delay after the oscillator becomes active. If the
RESET pin is low at the end of this 4064-cycle delay, the MCU will remain in the reset
condition until RESET goes high.
RESET
NOTES:
1. Internal timing signal and bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
OSC1
2
Internal
Clock
1
Internal
Address
Bus
1
V
DD
Internal
Data
Bus
1
Figure 4-3: Power-On Reset and RESET
t
RL
New
PCH
New
PCL
Op
Code
Op
Code
PCH
PCL
3
t
cyc
4064t
cyc
t
VDDR
Dummy
1FFF
New
PC
New
PC
1FFE
New
PC
New
PC
1FFE
1FFF
1FFE
Dummy
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