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参数资料
| 型号： | MC68HC05C5CP |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | DIP-40 |
| 文件页数： | 40/58页 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CP |
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Page 39
Section 7: Simple Input/Output Port
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
SECTION 7
SIMPLE SERIAL INPUT/OUTPUT PORT
This device includes a simple synchronous Serial I/O Port (SIOP). The SIOP is a three-
wire master/slave system including Serial Clock (SCK), Serial Data Input (SDI), and Serial
Data Output (SDO). A mask programmable option determines whether the SIOP is MSB
or LSB first.
7.1
SIGNAL FORMAT
7.1.1
SCK
The state of SCK between transmissions must be logic ’1’ for CPOL set and logic ’0’ for
CPOL clear. The first transition of SCK signals the beginning of a transmission. At this
time, the first bit of received data is accepted at the SDI pin and the first bit of transmitted
data is presented at the SDO pin. Data is captured at the SDI pin on the rising edge of
SCK. Subsequent falling edges shift the data and accept or present the next bit. The
transmission is ended upon the eighth rising edge of SCK. The maximum frequency of
SCK in slave mode is equal to E (bus clock) divided by 4. That is for a 4 MHz oscillator
input E becomes 2 MHz and the maximum SCK frequency is 500 KHz. There is no
minimum SCK frequency.
In master mode, the format is identical except that the SCK pin is an output and the shift
clock now originates internally. The master mode transmission frequency is fixed at E/4.
7.1.2
SDO
A mask programmable option will be included to allow data to be transmitted in either MSB
first format or LSB first format. In either case, the state of the SDO pin will always reflect
the value of the first bit received on the previous transmission if there was one. Upon
enabling the SIOP, SDO will always be driven to a logic one by the SIOP subsystem.
Figure 7-1: SIOP Block Diagram
8-BIT SHIFT REGISTER
D
Q
R
C
RESET
SDO
SCK
SDI
MSB/LSB MASK OPTION
DATA BUS
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